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NB3N551DR2G View Datasheet(PDF) - ON Semiconductor

Part NameDescriptionManufacturer
NB3N551DR2G 3.3 V / 5.0 V Ultra-Low Skew 1:4 Clock Fanout Buffer ON-Semiconductor
ON Semiconductor ON-Semiconductor
NB3N551DR2G Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
NB3N551
3.3 V / 5.0 V
Ultra-Low Skew
1:4 Clock Fanout Buffer
Description
The NB3N551 is a low skew 1to 4 clock fanout buffer, designed
for clock distribution in mind. The NB3N551 specifically guarantees
low outputtooutput skew. Optimal design, layout and processing
minimize skew within a device and from device to device.
The output enable (OE) pin threestates the outputs when low.
Features
Input/Output Clock Frequency up to 180 MHz
Low Skew Outputs (50 ps typical)
RMS Phase Jitter (12 kHz – 20 MHz): 43 fs (Typical)
Output goes to ThreeState Mode via OE
Operating Range: VDD = 3.0 V to 5.5 V
Ideal for Networking Clocks
Packaged in 8pin SOIC
Industrial Temperature Range
These are PbFree Devices
Q1
Q2
CLK
Q3
Q4
OE
Figure 1. Block Diagram
http://onsemi.com
8
1
SOIC8
D SUFFIX
CASE 751
MARKING
DIAGRAMS*
8
3N551
ALYW
G
1
3N551 = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
DFN8
MN SUFFIX
1
CASE 506AA
14
6K = Specific Device Code
M = Date Code
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
PIN CONNECTIONS
1
ICLK
2
Q1
3
Q2
4
Q3
8
OE
7
VDD
6
GND
5
Q4
ORDERING INFORMATION
Device
Package
Shipping
NB3N551DG
NB3N551DR2G
SOIC8
(PbFree)
SOIC8
(PbFree)
98 Units/Rail
2500/Tape & Reel
NB3N551MNR4G DFN8 1000/Tape & Reel
(PbFree)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2009
1
March, 2009 Rev. 3
Publication Order Number:
NB3N551/D
Direct download click here
 

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