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NB6L295MMNTXG View Datasheet(PDF) - ON Semiconductor

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NB6L295MMNTXG Datasheet PDF : 13 Pages
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NB6L295M
Q0/Q0
Q1/Q1
PD0 Delay
MSEL
PD1 Delay
SLOAD
PD0 Latch
0
PD1 Latch
1
SDATA
SCLK
11Bit Shift Register
Figure 7. Serial Data Interface, Shift Register, Data Latch, Programmable Delay Channels
Load Cycle Required for Each Channel
Serial Data Interface Loading
Loading the device through the 3 input Serial Data Interface (SDI) is accomplished by sending data into the SDIN pin by
using the SCLK input pin and latching the data with the SLOAD input pin. The 11bit SHIFT REGISTER shifts once per rising
edge of the SCLK input. The serial input SDIN must meet setup and hold timing as specified in the AC Characteristics section
of this document for each bit and clock pulse. The SLOAD line loads the value of the shift register on a LOWtoHIGH edge
transition (transparent state) into a data Latch register and latches the data with a subsequent HIGHtoLOW edge transition.
Further changes in SDIN or SCLK are not recognized by the latched register. The internal multiplexer states are set by the PSEL
and MSEL bits in the SHIFT register. Figure 6 shows the timing diagram of a typical load sequence. Input EN should be LOW
(enabled) prior to SDI programming, then pulled HIGH (disabled) during programming. After programming, the EN should
be returned LOW (enabled) for functional delay operation.
EN
SDIN
SCLK
SLOAD
ts SDIN to
SCLK
EN to SDIN
LSB
MSB
PSEL MSEL D0 D1 D2 D3 D4 D5 D6 D7 D8
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
EN to SLOAD
th SDIN to SCLK
ts SCLK to SLOAD
tH SCLK to SLOAD
Figure 8. SDI Programming Cycle Timing Diagram (Load Cycle 1 of 2)
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