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NB6L295MMNTXG View Datasheet(PDF) - ON Semiconductor

Part NameDescriptionManufacturer
NB6L295MMNTXG 2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential CML Outputs ON-Semiconductor
ON Semiconductor ON-Semiconductor
NB6L295MMNTXG Datasheet PDF : 13 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
2.5V / 3.3V Dual Channel
Programmable Clock/Data
Delay with Differential CML
MultiLevel Inputs w/ Internal Termination
The NB6L295M is a Dual Channel Programmable Delay Chip
designed primarily for Clock or Data deskewing and timing
adjustment. The NB6L295M is versatile in that two individual
variable delay channels, PD0 and PD1, can be configured in one of
two operating modes, a Dual Delay or an Extended Delay.
In the Dual Delay Mode, each channel has a programmable delay
section which is designed using a matrix of gates and a chain of
multiplexers. There is a fixed minimum delay of 3.2 ns per channel.
24 1
The Extended Delay Mode amounts to the additive delay of PD0
plus PD1 and is accomplished with the Serial Data Interface MSEL bit
set High. This will internally cascade the output of PD0 into the input
of PD1. Therefore, the Extended Delay path starts at the IN0/IN0
inputs, flows through PD0, cascades to the PD1 and outputs through
= Assembly Location
= Wafer Lot
= Year
= Work Week
= PbFree Package
(Note: Microdot may be in either location)
Q1/Q1. There is a fixed minimum delay of 6.0 ns for the Extended
Delay Mode.
*For additional marking information, refer to
Application Note AND8002/D.
The required delay is accomplished by programming each delay
channel via a 3pin Serial Data Interface, described in the application
section. The digitally selectable delay has an increment resolution of
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
typically 11 ps with a net programmable delay range of either 0 ns to
6 ns per channel in Dual Delay Mode; or from 0 ns to 11.2 ns for the
Extended Delay Mode.
The MultiLevel Inputs can be driven directly by differential
LVPECL, LVDS or CML logic levels; or by single ended LVPECL,
LVCMOS or LVTTL. A single enable pin is available to control both
inputs. The SDI input pins are controlled by LVCMOS or LVTTL
level signals. The NB6L295M 16 mA CML output contains
temperature compensation circuitry. This device is offered in a 4 mm x
4 mm 24pin QFN Pbfree package. The NB6L295M is a member of
the ECLinPS MAXfamily of high performance products.
Input Clock Frequency > 1.5 GHz with 210 mV
2.4 ps Typical Clock Jitter, RMS
Input Data Rate > 2.5 Gb/s
Programmable Delay Range: 0 ns to 6 ns per Delay
20 ps PkPk Typical Data Dependent Jitter
LVPECL, CML or LVDS Differential Input Compatible
LVPECL, LVCMOS, LVTTL Single Ended Input
Programmable Delay Range: 0 ns to 11.2 ns for
3Wire Serial Interface
Extended Delay Mode
Total Delay Range: 3.2 ns to 8.5 ns per Delay Channel
Total Delay Range: 6.2 ns to 16.6 ns in Extended Delay
Monotonic Delay: 11 ps Increments in 511 Steps
Linearity $20 ps, Maximum
100 ps Typical Rise and Fall Times
Operating Range: VCC = 2.375 V to 3.6 V
CML Output Level; 380 mV PeaktoPeak, Typical
Internal 50 W Input/Output Termination Provided
40°C to 85°C Ambient Operating Temperature
24Pin QFN, 4 mm x 4 mm
These are PbFree Devices*
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2010
January, 2010 Rev. 4
Publication Order Number:
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