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NB6L295MNG View Datasheet(PDF) - ON Semiconductor

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Description
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NB6L295MNG Datasheet PDF : 14 Pages
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NB6L295
VT0 IN0 IN0 VT0 GND VCC0
24 23 22 21 20 19
Exposed Pad
(EP)
VCC 1
18 Q0
EN 2
SLOAD 3
SDIN 4
NB6L295
17 Q0
16 VCC0
15 VCC1
SCLK 5
14 Q1
VCC 6
13 Q1
7 8 9 10 11 12
VT1 IN1 IN1 VT1 GND VCC1
Figure 2. Pinout: QFN24 (Top View)
Table 1. PIN DESCRIPTION
Pin Name
I/O
Description
1
VCC
Power Supply
Positive Supply Voltage for the Inputs and Core Logic
2
EN
LVCMOS/LVTTL Input
Input Enable/ Disable for both PD0 and PD1. LOW for enable, HIGH for disable, Open Pin Default
state LOW (37 kW pulldown resistor).
3
SLOAD
LVCMOS/LVTTL Input
Serial Load; This pin loads the configuration latches with the contents of the shift register. The
latches will be transparent when this signal is HIGH; thus, the data must be stable on the HIGH
toLOW transition of S_LOAD for proper operation. Open Pin Default state LOW (37 kW pulldown
resistor).
4
SDIN
LVCMOS/LVTTL Input
Serial Data In; This pin acts as the data input to the serial configuration shift register. Open Pin
Default state LOW (37 kW pulldown resistor).
5
SCLK
LVCMOS/LVTTL Input
Serial Clock In; This pin serves to clock the serial configuration shift register. Data from SDIN is
sampled on the rising edge. Open Pin Default state LOW (37 kW pulldown resistor).
6
VCC
Power Supply
Positive Supply Voltage for the Inputs and Core Logic
7
VT1
Internal 50 W Termination Pin for IN1
8
IN1
LVPECL, CML, LVDS Input Noninverted differential input. Note 1.
9
IN1
LVPECL, CML, LVDS Input Inverted differential input. Note 1.
10
VT1
Internal 50 W Termination Pin for IN1
11
GND
Power Supply
Negative Power Supply
12
VCC1
Power Supply
Positive Supply Voltage for the Q1/Q1 outputs, channel PD1
13
Q1
14
Q1
15
VCC1
LVPECL Output
LVPECL Output
Power Supply
Inverted Differential Output. Channel 1. Typically terminated with 50 W resistor to
VCC1 2.0 V.
Noninverted Differential Output. Channel 1. Typically terminated with 50 W resistor to
VCC1 2.0 V.
Positive Supply Voltage for the Q1/Q1 outputs, channel PD1
16
VCC0
Power Supply
Positive Supply Voltage for the Q0/Q0 outputs, channel PD0
17
Q0
18
Q0
19
VCC0
LVPECL Output
LVPECL Output
Power Supply
Inverted Differential Output. Channel 0. Typically terminated with 50 W resistor to
VCC0 2.0 V.
Noninverted Differential Output . Channel 0. Typically terminated with 50 W resistor to
VCC0 2.0 V.
Positive Supply Voltage for the Q0/Q0 outputs, channel PD0
20
GND
Power Supply
Negative Power Supply
21
VT0
Internal 50 W Termination Pin for IN0
22
IN0
LVPECL, CML, LVDS Input Inverted differential input. Note 1.
23
IN0
LVPECL, CML, LVDS Input Noninverted differential input. Note 1.
24
VT0
Internal 50 W Termination Pin for IN0
EP
Ground
The Exposed Pad (EP) on the QFN24 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heatsinking
conduit. The pad is electrically connected to GND and must be connected to GND on the PC
board.
1. In the differential configuration when the input termination pin (VTx/VTx) are connected to a common termination voltage or left open, and
if no signal is applied on INx/INx input then the device will be susceptible to selfoscillation.
2. All VCC, VCC0 and VCC1 Pins must be externally connected to the same power supply for proper operation. Both VCC0s are connected
to each other and both VCC1s are connected to each other: VCC0 and VCC1 are separate.
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