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NBC12429FNG View Datasheet(PDF) - ON Semiconductor

Part Name
Description
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NBC12429FNG Datasheet PDF : 22 Pages
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NBC12429, NBC12429A
Table 8. AC CHARACTERISTICS (VCC = 3.125 V to 5.25 V; TA = 0°C to 70°C (NBC12429), TA = 40°C to 85°C (NBC12429A))
(Note 6)
Symbol
Characteristic
Condition
Min
Max Unit
FMAXI
Maximum Input Frequency
S_CLOCK (Note 7)
Xtal Oscillator
10
MHz
10
20
FMAXO
Maximum Output Frequency
VCO (Internal)
FOUT
200
400 MHz
25
400
tjitter(pd)
Period Jitter @ 3.3 V
10000 WFMS
(See Table 13 for Typical Values)
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
25 psRMS
9.0
6.0
9.0
5.0
4.0
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
146 psPP
71
53
125
60
54
Period Jitter @ 5.0 V
10000 WFMS
(See Table 13 for Typical Values)
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
25 psRMS
9.0
6.0
10
6.0
5.0
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
168 psPP
69
57
133
49
108
tjitter(cyccyc) CycletoCycle @ 3.3 V
1000 WFMS
(See Table 13 for Typical Values)
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
20 psRMS
11
8.0
17
10
9.0
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
150 psPP
105
77
208
94
89
CycletoCycle @ 5.0 V
1000 WFMS
(See Table 13 for Typical Values)
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
25 psRMS
12
8.0
18
11
10
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
192 psPP
131
76
164
128
186
tLOCK
Maximum PLL Lock Time
10
ms
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
6. FOUT/FOUT outputs are terminated through a 50 W resistor to VCC 2.0 V.
7. 10 MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used
as a test clock in TEST_MODE 6.
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