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NBC12429 View Datasheet(PDF) - ON Semiconductor

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Description
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NBC12429 Datasheet PDF : 22 Pages
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NBC12429, NBC12429A
The following gives a brief description of the functionality of the NBC12429 and NBC12429A Inputs and Outputs. Unless
explicitly stated, all inputs are CMOS/TTL compatible with either pullup or pulldown resistors. The PECL outputs are capable
of driving two series terminated 50 W transmission lines on the incident edge.
Table 3. PIN FUNCTION DESCRIPTION
Pin Name
Function
INPUTS
XTAL1, XTAL2 Crystal Inputs
S_LOAD*
CMOS/TTL Serial Latch Input
(Internal Pulldown Resistor)
S_DATA*
S_CLOCK*
P_LOAD**
CMOS/TTL Serial Data Input
(Internal Pulldown Resistor)
CMOS/TTL Serial Clock Input
(Internal Pulldown Resistor)
CMOS/TTL Parallel Latch Input
(Internal Pullup Resistor)
M[8:0]**
N[1:0]**
OE**
OUTPUTS
FOUT, FOUT
TEST
POWER
VCC
PLL_VCC
GND
CMOS/TTL PLL Loop Divider
Inputs (Internal Pullup Resistor)
CMOS/TTL Output Divider Inputs
(Internal Pullup Resistor)
CMOS/TTL Output Enable Input
(Internal Pullup Resistor)
PECL Differential Outputs
CMOS/TTL Output
Positive Supply for the Logic
Positive Supply for the PLL
Negative Power Supply
Exposed Pad for QFN32 only
* When left Open, these inputs will default LOW.
** When left Open, these inputs will default HIGH.
Description
These pins form an oscillator when connected to an external seriesresonant
crystal.
This pin loads the configuration latches with the contents of the shift registers. The
latches will be transparent when this signal is HIGH; thus, the data must be stable
on the HIGHtoLOW transition of S_LOAD for proper operation.
This pin acts as the data input to the serial configuration shift registers.
This pin serves to clock the serial configuration shift registers. Data from S_DATA
is sampled on the rising edge.
This pin loads the configuration latches with the contents of the parallel inputs.
The latches will be transparent when this signal is LOW; therefore, the parallel
data must be stable on the LOWtoHIGH transition of P_LOAD for proper opera-
tion.
These pins are used to configure the PLL loop divider. They are sampled on the
LOWtoHIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB.
These pins are used to configure the output divider modulus. They are sampled
on the LOWtoHIGH transition of P_LOAD.
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of
runt pulse generation on the FOUT output.
These differential, positivereferenced ECL signals (PECL) are the outputs of the
synthesizer.
The function of this output is determined by the serial configuration bits T[2:0].
The positive supply for the internal logic and output buffer of the chip, and is con-
nected to +3.3 V or +5.0 V.
This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V.
These pins are the negative supply for the chip and are normally all connected to
ground.
The Exposed Pad (EP) on the QFN32 package bottom is thermally connected to
the die for improved heat transfer out of package. The exposed pad must be at-
tached to a heatsinking conduit. The pad is electrically connected to GND.
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