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NB100LVEP222FAG View Datasheet(PDF) - ON Semiconductor

Part Name
Description
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NB100LVEP222FAG Datasheet PDF : 10 Pages
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NB100LVEP222
VCC0
Qb2
Qb2
Qb1
Qb1
Qb0
Qb0
VCC0
Qa1
Qa1
Qa0
Qa0
VCC0
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40
26
41
25
42
24
43
23
44
22
45
21
46
NB100LVEP222
20
47
19
48
18
49
17
50
16
51
15
52
14
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Qd0
Qd0
Qd1
Qd1
Qd2
Qd2
Qd3
Qd3
Qd4
Qd4
Qd5
Qd5
VCC0
All VCC, VCC0, and VEE pins must be externally connected to appropriate Power Supply to guarantee proper operation.VCC pin internally
connected to VCC0 pins. The thermally conductive exposed pad on package bottom (see package case drawing) must be attached to a
heat−sinking conduit. This exposed pad is electrically connected to VEE internally.
Figure 1. 52−Lead LQFP Pinout (Top View)
PIN DESCRIPTION
PIN
CLK0*, CLK0**
CLK1*, CLK1**
CLK_Sel*
MR*
Qa0:1, Qa0:1
Qb0:2, Qb0:2
Qc0:3, Qc0:3
Qd0:5, Qd0:5
fseln*
VBB
VCC, VCC0
VEE***
NC
FUNCTION
ECL Differential Input Clock
ECL Differential Input Clock
ECL Clock Select
ECL Master Reset
ECL Differential Outputs
ECL Differential Outputs
ECL Differential Outputs
ECL Differential Outputs
ECL 1 or 2 Select
Reference Voltage Output
Positive Supply, VCC = VCC0
Negative Supply
No Connect
FUNCTION TABLE
Input
Function
L
H
MR
CLK_Sel
fseln
Active
CLK0
÷1
Reset
CLK1
÷2
* Pins will default LOW when left open.
** Pins will default HIGH when left open.
*** The thermally conductive exposed pad on the bottom of
the package is electrically connected to VEE internally.
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