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HYS64V16220GU View Datasheet(PDF) - Infineon Technologies

Part Name
Description
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HYS64V16220GU Datasheet PDF : 17 Pages
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HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
SPD-Table for PC100 Modules (cont’d)
Byte# Description
SPD
Entry
Value
Hex
8M×64 8M×64 8M×72 16M×64 16M×64 16M×72
-8
-8B
-8
-8
-8B
-8
15 Minimum clock
tCCD = 1
01
01
01
01
01
01
delay for back-to- CLK
back random
column address
16 Burst Length
supported
1, 2, 4, 8 & 8F
8F
8F
8F
8F
8F
full page
17 Number of SDRAM 4
banks
04
04
04
04
04
04
18 Supported CAS
CAS
06
06
06
06
06
06
Latencies
latency =
2&3
19 CS Latencies
CS
01
01
01
01
01
01
latency = 0
20 WE Latencies
Write
01
01
01
01
01
01
latency = 0
21 SDRAM DIMM
non
00
00
00
00
00
00
module attributes buffered/
non reg.
22 SDRAM Device
VCC tol ± 06
06
06
06
06
06
Attributes: General 10%
23 Min. Clock Cycle 10.0/12.0 A0
C0
A0
A0
C0
A0
Time at CAS
ns
Latency = 2
24 Max. data access 6.0/7.0 ns 60
70
60
60
60
60
time from Clock for
CL = 2
25 Minimum Clock
not
FF
FF
FF
FF
FF
FF
Cycle Time at
supported
CL = 1
26 Maximum Data
not
FF
FF
FF
FF
FF
FF
Access Time from supported
Clock at CL = 1
27 Minimum Row
20/30 ns 14
1E
14
14
1E
14
Precharge Time
28 Minimum Row
16/20 ns 10
14
10
10
14
10
Active to Row
Active delay tRRD
Semiconductor Group
13
1998-08-01
 

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