When using the Automatic Block Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verify command is required). The margin
voltages are internally generated in the same manner
as when the standard erase verify command is used.
The Automatic set-up block erase command is a com-
mand only operation that stages the device for auto-
matic electrical erasure of selected blocks in the array.
Automatic set-up block erase is performed by writing
20H to the command register.
To enter automatic block erase, the user must write
the command D0H to the command register. Block
addresses are loaded into internal register on the 2nd
falling edge of WE. Each successive block load cycles,
started by the falling edge of WE, must begin within
30us from the rising edge of the preceding WE.
Otherwise, the loading period ends and internal auto
block erase cycle starts. When the data on DQ7 is "1"
and the data on DQ6 stops toggling for two
consecutive read cycles, at which time auto erase
ends and the device returns to the Read mode.
Refer to page 2 for detailed block address.
SET-UP AUTOMATIC PROGRAM/PROGRAM
The Automatic Set-up Program is a command-only
operation that stages the device for automatic pro-
gramming. Automatic Set-up Program is performed by
writing 40H to the command register.
Once the Automatic Set-up Program operation is per-
formed, the next WE pulse causes a transition to an
active programming operation. Addresses are
internally latched on the falling edge of the WE pulse.
Data is internally latched on the rising edge of the WE
pulse. The rising edge of WE also begins the
programming operation. The system is not required to
provide further controls or timings. The device will
automatically provide an adequate internally
generated program pulse and verify margin. The
automatic programming operation is completed when
the data read on DQ6 stops toggling for two
consecutive read cycles and the data on DQ7 and
DQ6 are equivalent to data written to these two bits, at
which time the device returns to the Read mode (no
program verify command is required).
A reset command is provided as a means to safely
abort the erase- or program-command sequences.
Following either set-up command (erase or program)
with two consecutive writes of FFH will safely abort the
operation. Memory contents will not be altered. Should
program-fail or erase-fail happen, two consecutive
writes of FFH will reset the device to abort the
operation. A valid command must then be written to
place the device in the desired state.
WRITE OPERATON STATUS
The MX28F2000P features a "Toggle Bit" as a method
to indicate to the host sytem that the Auto Program/
Erase algorithms are either in progress or completed.
While the Automatic Program or Erase algorithm is in
progress, successive attempts to read data from the
device will result in DQ6 toggling between one and
zero. Once the Automatic Program or Erase algorithm
is completed, DQ6 will stop toggling and valid data will
be read. The toggle bit is valid after the rising edge of
the second WE pulse of the two write pulse sequences.
The MX28F2000P also features Data Polling as a
method to indicate to the host system that the
Automatic Program or Erase algorithms are either in
progress or completed.
While the Automatic Programming algorithm is in op-
eration, an attempt to read the device will produce the
complement data of the data last written to DQ7. Upon
completion of the Automatic Program algorithm an
attempt to read the device will produce the true data
last written to DQ7. The Data Polling feature is valid
after the rising edge of the second WE pulse of the two
write pulse sequences.
REV. 1.5, OCT 29, 1998