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MX28F2000P View Datasheet(PDF) - Macronix International

Part NameDescriptionManufacturer
MX28F2000P 2M-BIT [256K x 8] CMOS FLASH MEMORY MCNIX
Macronix International MCNIX
MX28F2000P Datasheet PDF : 33 Pages
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MX28F2000P
READ COMMAND
While VPP is high, for erasure and programming,
memory contents can also be accessed via the read
command. The read operation is initiated by writing
00H into the command register. Microprocessor read
cycles retrieve array data. The device remains en-
abled for reads until the command register contents
are altered.
The default contents of the register upon VPP power-
up is 00H. This default value ensures that no spurious
alteration of memory contents occurs during the VPP
power transition. Where the VPP supply is hard-wired
to the MX28F2000P, the device powers up and
remains enabled for reads until the command register
contents are changed.
SILICON-ID-READ COMMAND
Flash-memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer- and device-codes must be accessible
while the device resides in the target system. PROM
programmers typically access signature codes by rais-
ing A9 to a high voltage. However, multiplexing high
voltage onto address lines is not a desired system-
design practice.
The MX28F2000P contains a Silicon-ID-Read opera-
tion to supplement traditional PROM-programming
methodology. The operation is initiated by writing 90H
into the command register. Following the command
write, a read cycle from address 0000H retrieves the
manufacturer code of C2H. A read cycle from address
0001H returns the device code of 2AH.
SET-UP AUTOMATIC CHIP ERASE/ERASE
COMMANDS
The automatic chip erase does not require the device
to be entirely pre-programmed prior to excuting the
Automatic set-up erase command and Automatic chip
erase command. Upon executing the Automatic chip
erase command, the device automatically will program
and verify the entire memory for an all-zero data
pattern. When the device is automatically verified to
contain an all-zero pattern, a self-timed chip erase and
verify begin. The erase and verify operations are
complete when the data on DQ7 is "1" at which time the
device returns to the Read mode. The system is not
required to provide any control or timing during these
operations.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when
adequate erase margin has been achieved for the
memory array(no erase verify command is required).
The margin voltages are internally generated in the
same manner as when the standard erase verify
command is used.
The Automatic set-up erase command is a command-
only operation that stages the device for automatic
electrical erasure of all bytes in the array. Automatic
set-up erase is performed by writing 30H to the
command register.
To command automatic chip erase, the command 30H
must be written again to the command register. The
automatic chip erase begins on the rising edge of the
WE and terminates when the data on DQ7 is "1" and
the data on DQ6 stops toggling for two consecutive
read cycles, at which time the device returns to the
Read mode.
SET-UP AUTOMATIC BLOCK ERASE/ERASE
COMMANDS
The automatic block erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic set-up block erase command and
Automatic block erase command. Upon executing the
Automatic block erase command, the device automati-
cally will program and verify the block(s) memory for an
all-zero data pattern. The system is not required to
provide any controls or timing during these operations.
When the block(s) is automatically verified to contain
an all-zero pattern, a self-timed block erase and verify
begin. The erase and verify operations are complete
when the data on DQ7 is "1" and the data on DQ6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode. The system is
not required to provide any control or timing during
these operations.
P/N: PM0380
REV. 1.5, OCT 29, 1998
8
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