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25L1605 View Datasheet(PDF) - Macronix International

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MX25L1605D
MX25L3205D
MX25L6405D
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress
(WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets
0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP3,
BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP3, BP2, BP1,
BP0 all set to "0".
(12) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must
execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If the eight least significant address
bits (A7-A0) are not all 0, all transmitted data which goes beyond the end of the current page are programmed from the start
address if the same page (from the address whose 8 least significant address bits (A7-A0) are all 0). The CS# must keep
during the whole Page Program cycle. The CS# must go high exactly at the byte boundary( the latest eighth of address
byte been latched-in); otherwise, the instruction will be rejected and not executed. If more than 256 bytes are sent to the
device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than
256 bytes are sent to the device, the data is programmed at the request address of the page without effect on other address
of the same page.
The sequence of issuing PP instruction is: CS# goes low-> sending PP instruction code-> 3-byte address on SI-> at least
1-byte on data on SI-> CS# goes high. (see Figure 20)
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress
(WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and
sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by
BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.
(13) Continuously program mode (CP mode)
The CP mode may enhance program performance by automatically increasing address to the next higher address after each
byte data has been programmed.
The Continuously program (CP) instruction is for multiple byte program to Flash. A write Enable (WREN) instruction must
execute to set the Write Enable Latch(WEL) bit before sending the Continuously program (CP) instruction. CS# requires
to go high before CP instruction is executing. After CP instruction and address input, two bytes of data is input sequentially
from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address range with A0=0 and second byte
data with A0=1. If only one byte data is input, the CP mode will not process. If more than two bytes data are input, the
additional data will be ignored and only two byte data are valid. The CP program instruction will be ignored and not affect
the WEL bit if it is applied to a protected memory area. Any byte to be programmed should be in the erase state (FF) first.
It will not roll over during the CP mode, once the last unprotected address has been reached, the chip will exit CP mode
and reset write Enable Latch bit (WEL) as "0" and CP mode bit as "0". Please check the WIP bit status if it is not in write
progress before entering next valid instruction. During CP mode, the valid commands are CP command (AD hex), WRDI
command (04 hex), RDSR command (05 hex), RDPR command (A1 hex), and RDSCUR command (2B hex). And the WRDI
command is valid after completion of a CP programming cycle, which means the WIP bit=0.
The sequence of issuing CP instruction is : CS# high to low-> sending CP instruction code-> 3-byte address on SI-> Data
Byte on SI->CS# goes high to low-> sending CP instruction......-> last desired byte programmed or sending Write Disable
(WRDI) instruction to end CP mode-> sending RDSR instruction to verify if CP mode is ended. (see Figure of CP mode
timing waveform)
Three methods to detect the completion of a program cycle during CP mode:
1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode.
P/N: PM1290
REV. 1.4, OCT. 01, 2008
23
 

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