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25L1605 View Datasheet(PDF) - Macronix International

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25L1605 Datasheet PDF : 56 Pages
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MX25L1605D
MX25L3205D
MX25L6405D
Note: If SRWD bit=1 but WP#/ACC is low, it is impossible to write the Status Register even if the WEL bit has previously
been set. It is rejected to write the Status Register and not be executed.
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP#/ACC is low (or WP#/ACC is low before SRWD bit=1), it enters the hardware protected
mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and
hardware protected mode by the WP#/ACC to against data modification.
Note: to exit the hardware protected mode requires WP#/ACC driving high once the hardware protected mode is entered.
If the WP#/ACC pin is permanently connected to high, the hardware protected mode can never be entered; only can use
software protected mode via BP3, BP2, BP1, BP0.
(6) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling
edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically
increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
READ instruction. The address counter rolls over to 0 when the highest address has been reached.
The sequence of issuing READ instruction is: CS# goes low-> sending READ instruction code-> 3-byte address on SI
-> data out on SO-> to end READ operation can use CS# to high at any time during data out. (see Figure. 17)
(7) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of
each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location.
The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory
can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has
been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low-> sending FAST_READ instruction code-> 3-byte
address on SI-> 1-dummy byte address on SI->data out on SO-> to end FAST_READ operation can use CS# to high at
any time during data out. (see Figure. 18)
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(8) 2 x I/O Read Mode (2READ)
The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of
SCLK, and data of every two bits(interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency
fT. The first address byte can be at any location. The address is automatically increased to the next higher address after
each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter
rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/
data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes lowsending 2READ instruction24-bit address interleave
on SIO1 & SIO08-bit dummy interleave on SIO1 & SIO0data out interleave on SIO1 & SIO0to end 2READ
operation can use CS# to high at any time during data out (see Figure of 2 x I/O Read Mode Timing Waveform)
P/N: PM1290
REV. 1.4, OCT. 01, 2008
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