IS61LV6424 View Datasheet(PDF) - Integrated Silicon Solution
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IS61LV6424 Datasheet PDF : 10 Pages
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IS61LV6424
WRITE CYCLE NO. 3(1) (WE Controlled: OE I S LOW DURING WRITE CYLE)
t WC
ADDRESS
VALID ADDRESS
1
OE LOW
CE1 LOW
t HA
2
CE2 HIGH
t VW
3
V/S
t AW
t PWE2
WE
4
t SA
t HZWE
t LZWE
DOUT
DATA UNDEFINED
HIGH-Z
5
t SD
t HD
DIN
DATAIN VALID
6
Note:
1. The internal Write time is defined by the overlap of CE1 = LOW, CE2 = HIGH and WE = LOW. All signals must be in valid
states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is
referenced to the rising or falling edge of the signal that terminates the Write.
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Integrated Circuit Solution Inc.
AHSR012-0D
S2-103
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