MT9M111 View Datasheet(PDF) - Micron Technology
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PRELIMINARY
MT9M111
SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Functional Overview
The MT9M111 is a fully-automatic, single-chip
camera, requiring only a power supply, lens and clock
source for basic operation. Output video is streamed
via a parallel 8-bit DOUT port, shown in Figure 1 on
page 8. The output pixel clock is used to latch data,
while FRAME_VALID and LINE_VALID signals indi-
cate the active video. The MT9M111 internal registers
are configured using a two-wire serial interface.
The device can be put in low-power sleep mode by
asserting the standby pin and shutting down the clock.
Output pins can be tri-stated by de-asserting the OE#
pin. Both tri-stating output pins and entry in standby
mode also can be achieved via two-wire serial inter-
face register writes.
The MT9M111 accepts input clocks up to 54 MHz,
delivering up to 15 fps for SXGA resolution images, and
up to 30 fps for QSXGA (full field-of-view, sensor pixel
skipping) images. The device also supports a low-
power preview configuration that delivers SXGA
images at 7.5 fps and QSXGA images at 30 fps. The
device can be programmed to slow the frame rate in
low-light conditions to achieve longer exposures and
better image quality.
Internal Architecture
Internally, the MT9M111 consists of a sensor core
and an IFP. The IFP is divided in two sections: the col-
orpipe (CP), and the camera controller (CC). The sen-
sor core captures raw Bayer-encoded images that are
then input in the IFP. The CP section of the IFP pro-
cesses the incoming stream to create interpolated,
color-corrected output, and the CC section controls
the sensor core to maintain the desired exposure and
color balance, and to support snapshot modes. The
sensor core, CP, and CC registers are grouped in three
separate address spaces, shown in Figure 2. When
accessing internal registers via the two-wire serial
interface, select the desired address space by program-
ming the R240 shared register.
The MT9M111 accelerates mode switching with
hardware-assisted context switching, and supports
taking snapshots, flash snapshots, and video clips
using a configurable sequencer.
The MT9M111 supports a range of color formats
derived from four primary color representations:
YCbCr, RGB, raw Bayer (unprocessed, directly from
the sensor), and processed Bayer (Bayer format data
regenerated from processed RGB). The device also
supports a variety of output signaling/timing options:
• Standard FRAME_VALID/LINE_VALID video
interface with gated pixel clocks
• Standard video interface with uniform clocking
• ITU-R BT.656 marker-embedded video interface
with either gated or uniform pixel clocking.
Register Notation
The following register address notations are used in
this document:
• R<decimal address>:<address page>
Example: R9:0—Shutter width register in sensor
page (page 0). Used to uniquely specify a register.
• R<decimal address>
Example: R240—Page address register. Used when
the register address is the same in all three pages or
when by context the address page is understood.
• 0x<2 digit hex address>
Example: 0xF0—Page address register. Used when
the register address is the same in all three pages, or
when by context the address page is understood.
09005aef8136743e pdf/09005aef8136761e zip
MT9M111__SOC1310__2.fm - Rev. C 10/04 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
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