MT9M111 View Datasheet(PDF) - Micron Technology
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MT9M111 Datasheet PDF : 0 Pages
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PRELIMINARY
MT9M111
SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 12: Sensor Core Register Descriptions (continued)
BIT FIELD
DESCRIPTION
DEFAULT SYNCED TO BAD READ/
(HEX) FRAME START FRAME WRITE
Bits 14:0
Number of blank rows in a frame when Context A is chosen
0x11
Y
Vertical
(bit 1, Reg0x0C8 = 1). This number must be equal to or larger
Blanking A than the number of dark rows read out in a frame specified by
Reg0x022.
N
W
R9:0—0X009 - SHUTTER WIDTH
Bits 15:0
Integration time in number of rows. In addition to this
0x219
Y
Shutter Width register, the shutter delay register (Reg0x0C) and the overhead
time influences the integration time for a given row time.
N
W
R10:0—0X00A - ROW SPEED
Bits 15:13
Bit 8
Invert Pixel
Clock
Bits 7:4
Delay Pixel
Clock
Bits 3:0
Pixel Clock
Speed
Reserved.
—
Invert pixel clock. When set, LINE_VALID, FRAME_VALID, and
0x0
DATA_OUT are set to the falling edge of PIXCLK. When clear,
they are set to the rising edge if there is no pixel clock delay.
Delay PIXCLK in half-master-clock cycles. When set, the pixel
0x1
clock can be delayed in increments of half-master- clock cycles
compared to the synchronization of FRAME_VALID,
LINE_VALID, and DATA_OUT.
Pixel clock period in master clocks when full-power readout
0x1
mode is used (Reg0x020/0x021, bit 10 = 0). In this case, the ADC
clock has twice the clock period. If low-power readout mode is
used, the pixel clock period is automatically doubled, so the
ADC clock period remains the same for one programmed
register value. The value “0” is not allowed, and “1” is used
instead.
—
—
—
N
0
W
N
0
W
Y
YM
W
R11:0—0X00B - EXTRA DELAY
Bits 13:0
Extra blanking inserted between frames specified in pixel
0x0
Y
0
W
Extra Delay clocks. Can be used to get a more exact frame rate. For
integration times less than a frame, however, it might affect
the integration times for parts of the image.
R12:0—0X00C - SHUTTER DELAY
Bits 10:0
The amount of time from the end of the sampling sequence to 0x0
Y
N
W
Shutter Delay the beginning of the pixel reset sequence. This variable is
automatically halved in low-power readout mode, so the time
in use remains the same. This register has an upper value
defined by the fact that the reset needs to finish prior to
readout of that row to prevent changes in the row time.
R13:0—0X00D - RESET
Bit 15
0: Normal operation, updates changes to registers that affect 0x0
N
0
W
Synchronize image brightness at the next frame boundary (integration
Changes
time, integration delay, gain, horizontal blanking and vertical
blanking, window size, row/column skip, or row mirror.
1: Do not update any changes to these settings until this bit is
returned to “0.” All registers that are frame synchronized are
affected by this bit setting.
Bit 9
When set, a forced restart occurs when a bad frame is
0x0
N
0
W
Restart Bad detected. This can shorten the delay when waiting for a good
Frames
frame because the delay when masking out a bad frame is the
integration time rather than the full frame time.
09005aef8136743e pdf/09005aef8136761e zip
MT9M111__SOC1310__2.fm - Rev. C 10/04 EN
40
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
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