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MT46V128M8 View Datasheet(PDF) - Micron Technology

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Description
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MT46V128M8
Micron
Micron Technology Micron
MT46V128M8 Datasheet PDF : 74 Pages
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PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Table 11: Clock Input Operating Conditions
0°C £ TA £ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
Notes: 1–5, 15, 16, 30; notes appear on page 54-57
PARAMETER/CONDITION
Clock Input Mid-Point Voltage; CK and CK#
Clock Input Voltage Level; CK and CK#
Clock Input Differential Voltage; CK and CK#
Clock Input Differential Voltage; CK and CK#
Clock Input Crossing Point Voltage; CK and CK#
SYMBOL
VMP(DC)
VIN(DC)
VID(DC)
VID(AC)
VIX(AC)
MIN
MAX
UNITS
1.15
1.35
V
-0.3
VDDQ + 0.3
V
0.36
VDDQ + 0.6
V
0.7
VDDQ + 0.6
V
0.5 x VDDQ - 0.2 0.5 x VDDQ + 0.2 V
NOTES
6, 9
6
6, 8
8
9
2.80V
Figure 32: SSTL_2 Clock Input
Maximum Clock Level5
CK#
1.45V
1.25V
1.05V
X
X
VMP (DC)1 VIX (AC)2
3
VID (DC)
4
VID (AC)
CK
- 0.30V
Minimum Clock Level5
NOTE:
1. This provides a minimum of 1.15V to a maximum of 1.35V, and is always half of VDDQ.
2. CK and CK# must cross in this region.
3. CK and CK# must meet at least VID(DC) min when static and is centered around VMP(DC)
4. CK and CK# must have a minimum 700mv peak to peak swing.
5. CK or CK# may not be more positive than VDDQ+ 0.3V or more negative than Vss - 0.3V.
6. For AC operation, all DC clock requirements must also be satisfied.
7. Numbers in diagram reflect nominal values.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
47
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
 

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