Transmitter
Figure 31: Input Voltage Waveform
VDDQ (2.3V minimum)
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
VOH(MIN) (1.670V1 for SSTL2 termination)
System Noise Margin (Power/Ground,
Crosstalk, Signal Integrity Attenuation)
1.560V
VIHAC
1.400V
1.300V
1.275V
1.250V
1.225V
1.200V
1.100V
VIHDC
VREF +AC Noise
VREF +DC Error
VREF -DC Error
VREF -AC Noise
VILDC
0.940V
VINAC - Provides margin
between VOL (MAX) and VILAC
VOL (MAX)
(0.83V2 for SSTL2 termination)
VSSQ
Receiver
VILAC
NOTE: 1. VOH (MIN) with test load is 1.927V
2. VOL (MAX) with test load is 0.373V
3. Numbers in diagram reflect nomimal
values utilizing circuit below.
VTT
25Ω
25Ω
Reference
Point
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
46
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©2003 Micron Technology. Inc.