MT46V128M8 View Datasheet(PDF) - Micron Technology
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MT46V128M8 Datasheet PDF : 74 Pages
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Table 2: Burst Definition
BURST
LENGTH
STARTING
COLUMN
ADDRESS
2
A0
0
1
4
A1 A0
00
01
10
11
8
A2 A1 A0
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
ORDER OF ACCESSES WITHIN A
BURST
TYPE=
SEQUENTIAL
TYPE=
INTERLEAVED
0-1
0-1
1-0
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
NOTE:
1. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
2. For a burst length of two, A1-Ai select the two-
data-element block; A0 selects the first access
within the block.
3. For a burst length of four, A2-Ai select the four-
data-element block; A0-A1 select the first access
within the block.
4. For a burst length of eight, A3-Ai select the eight-
data-element block; A0-A2 select the first access
within the block.
Read Latency
The READ latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2, or 2.5 clocks, as shown in Figure 6.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 3
indicates the operating frequencies at which each CAS
latency setting can be used.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
CK#
CK
COMMAND
DQS
DQ
CK#
CK
COMMAND
DQS
DQ
Figure 6: CAS Latency
T0
T1
T2 T2n
T3 T3n
READ
NOP
NOP
NOP
CL = 2
T0
READ
T1
T2 T2n T3 T3n
NOP
NOP
NOP
CL = 2.5
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDQSCK
TRANSITIONING DATA
DON’T CARE
Table 3: CAS Latency (CL)
SPEED
-75
ALLOWABLE OPERATING
CLOCK FREQUENCY (MHZ)
CL = 2
75 £ f £ 100
CL = 2.5
75 £ f £ 133
Operating Mode
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7-A13
each set to zero, and bits A0-A6 set to the desired val-
ues. A DLL reset is initiated by issuing a MODE REGIS-
TER SET command with bits A7 and A9-A13 each set to
zero, bit A8 set to one, and bits A0-A6 set to the desired
values. Although not required by the Micron device,
JEDEC specifications recommend when a LOAD
MODE REGISTER command is issued to reset the DLL,
it should always be followed by a LOAD MODE REGIS-
TER command to select normal operating mode.
All other combinations of values for A7-A13 are
reserved for future use and/or test modes. Test modes
and reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
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