datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

74ACT2708PC View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
74ACT2708PC
Fairchild
Fairchild Semiconductor Fairchild
74ACT2708PC Datasheet PDF : 13 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Mode 3: With FIFO Full, Shift-In is Held HIGH
in Anticipation of an Empty Location
Sequence of Operation
1. The FIFO is initially full and Shift-In goes HIGH. OR is
initially HIGH. Shift-Out is LOW. IR is LOW.
2. Shift-Out is pulsed HIGH, Shift-Out pulse propagates
and the first data word is latched on the rising edge of
SO. OR falls on this edge. On the falling edge of SO,
the second data word appears after propagation delay
tD. New data is written into the FIFO after SO goes
LOW.
3. Input Ready goes HIGH one fall-through time, tFT, after
the falling edge of SO. Also, HF goes HIGH one tOF
after SO falls, indicating that the FIFO is no longer full.
4. IR returns LOW pulse width t IP after rising and shifting
new data in. Also, HF returns LOW pulse width t3F after
rising, indicating the FIFO is once more full.
5. Shift-In is brought LOW to complete the shift-in process
and maintain normal operation.
Note: MR and FULL are HIGH; OE is LOW.
FIGURE 3. Modes of Operation Mode 3
www.fairchildsemi.com
6
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]