TDA8763M/3/C4 View Datasheet(PDF) - Philips Electronics

Part Name

Description

View to exact match

TDA8763M/3/C4

10-bit high-speed low-power ADC with internal reference regulator

Philips Electronics 

Philips Semiconductors

10-bit high-speed low-power ADC with

internal reference regulator

Product specification

TDA8763

3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities

of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to

pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3.

a) The current flowing into the resistor ladder is IL = R-----O---V-B---R-+---T--R--–---L--V--+--R---R-B---O----T- and the full-scale input range at the converter,

to cover code 0 to code 1023, is VI = RL × IL = R-----O----B----+-----RR-----LL----+-----R----O----T- × (V RT – VRB ) = 0˙.848 × (V RT – VRB )

b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio

R-----O----B----+-----RR-----LL----+-----R----O----T- will be kept reasonably constant from device to device. Consequently variation of the output

codes at a given input voltage depends mainly on the difference VRT − VRB and its variation with temperature and

supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the

matching between each of them is then optimized.

4. EG = --(--V----1---0--2---3----–V----V-i--(--0p--)-–----p–---)-V-----i--(--p---–----p---) × 100

5. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.

No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.

6. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale

input (square wave signal) in order to sample the signal and obtain correct output data.

7. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent

fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency

(NYQUIST frequency). Conversion to signal-to-noise ratio: SINAD = EB × 6.02 + 1.76 dB.

8. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two

input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter.

9. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a

digital-to-analog converter.

10. Output data acquisition: the output data is available after the maximum delay time of td(max). For 50 MHz version it is

recommended to have the lowest possible output load.

1999 Jan 06

handbook, halfpage

VRT

VRM

VRB

RLAD

ROT

RL

IL

code 1023

code 0

ROB

MGD281

Fig.3 Explanation of note 3.

11

Share Link: