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TDA8763AM/4 View Datasheet(PDF) - Philips Electronics

Part Name
Description
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TDA8763AM/4
Philips
Philips Electronics Philips
TDA8763AM/4 Datasheet PDF : 24 Pages
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Philips Semiconductors
10-bit high-speed low-power ADC
Product specification
TDA8763A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
TWO-TONE; note 8
TTIR
two-tone intermodulation
rejection
fclk = 40 MHz
69
dB
BIT ERROR RATE
BER
bit error rate
DIFFERENTIAL GAIN; note 9
Gdiff
differential gain
fclk = 50 MHz;
fi = 4.43 MHz;
VI = ±16 LSB at code 512
fclk = 40 MHz;
PAL modulated ramp
1013
0.8
times/
sample
%
DIFFERENTIAL PHASE; note 9
ϕdiff
differential phase
fclk = 40 MHz;
0.4
deg
PAL modulated ramp
Timing (fclk = 40 MHz; CL = 15 pF); see Fig.4; note 10
tds
sampling delay time
th
output hold time
td
output delay time
VCCO = 4.75 V
VCCO = 3.15 V
CL
digital output load capacitance
3
ns
4
ns
10
13
ns
12
15
ns
15
pF
3-state output delay times; see Fig.5
tdZH
enable HIGH
tdZL
enable LOW
tdHZ
disable HIGH
tdLZ
disable LOW
5.5
8.5
ns
12
15
ns
19
24
ns
12
15
ns
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 0.5 ns.
2. Analog input voltages producing code 0 up to and including code 1023:
a) Voffset(B) (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00
and the reference voltage BOTTOM (VRB) at Tamb = 25 °C.
b) Voffset(T) (voltage offset TOP) is the difference between reference voltage TOP (VRT) and the analog input which
produces data outputs equal to code 1023 at Tamb = 25 °C.
1999 Jan 06
10
 

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