DAC10
LOW-TO-HIGH SETTLING VL = 16.500V ؎0.001V
HIGH-TO-LOW SETTLING VL = 0.500V ؎0.001V
VL
0.500V ؎0.001V
+15V
51⍀
5
14
D.U.T.
4
15 16 18
3 17 1 2
0.01F
+15V
1F
+15V
2
6
REF-01 5
4
2.5k⍀ –15V
2.5k⍀
0.01F
10k⍀
0.1F
4k⍀
10F
IN5711
0.1F
10F
0.01F 4.7F
2N918
2N918
2k⍀
1M⍀
1/4W, 5% –15V
CARBON
1F
1k⍀
4.7F
0.01F
VO
499k⍀
1/4W, 5% CARBON
–15V
1/2 LSB SETTLING = 7.8mV
–15V
NOTES:
1. CASE OF 2N918s MUST BE GROUNDED.
2. RESISTORS ARE 1/4W MF, 1% UNLESS OTHERWISE SPECIFIED.
3. USE FET PROBE (7A11 SCOPE PLUGIN).
Figure 14. Settling Time Measurement
175mV
RL
4 IO
DAC10
IO
OP01
EO
2
0 TO +IFR ؋ RL
IFR
=
1023
1024
؋
2
؋
IREF
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE
LOGIC DAC), CONNECT INVERTING INPUT OF OP AMP TO
IO (PIN 2); CONNECT IO (PIN 4) TO GROUND.
Figure 15. Positive Low Impedance Output Operation
DAC10
4 IO
IO
2
OP15
EO
RL
0 TO –IFR ؋ RL
IFR
=
1023
1024
؋
2
؋
IREF
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE
LOGIC DAC), CONNECT NOINVERTING INPUT OF OP AMP TO
IO PIN 2); CONNECT IO (PIN 4) TO GROUND.
Figure 16. Negative Low Impedance Output Operation
TTL
VTH = +1.4V
DAC10
VLC
1
+15V
9.1k⍀
VTH = VLC +1.4V
+15V CMOS
VTH = +7.6V
VLC
6.2k⍀
0.1F
ECL
13k⍀
2N3904
"A"
3k⍀
39k⍀
2N3904
TO PIN 1
VLC
6.2k⍀
–5.2V
Figure 17. Interfacing with Various Logic Families
REV. D
–7–