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AD9060SZ View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
AD9060SZ 10-Bit 75 MSPS A/D Converter ADI
Analog Devices ADI
AD9060SZ Datasheet PDF : 12 Pages
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AD9060
ANALOG
INPUT
ENCODE
ENCODE
DATA
OUTPUT
N
ta
N
tOD
N+1
N+1
DATA FOR N
DATA FOR N + 1
ta – Aperture Delay
tOD – Output Delay
AD9060 Timing Diagram
Timing
In the AD9060, the rising edge of the ENCODE signal triggers
the A/D conversion by latching the comparators. (See the
AD9060 Timing Diagram.) These ENCODE and ENCODE
signals are ECL compatible and should be driven differentially.
Jitter on the ENCODE signal will raise the noise floor of the
converter. Differential signals, with fast clean edges, will reduce
the jitter in the signal and allow optimum ac performance. In
applications with a fixed, high frequency encode rate, converter
performance is also improved (jitter reduced) by using a crystal
oscillator as the system clock.
The AD9060 units are designed to operate with a 50% duty
cycle encode signal; adjustment of the duty cycle may improve
the dynamic performance of individual devices. Since the EN-
CODE and ENCODE signals are differential, the logic levels are
not critical. Users should remember, however, that reduced logic
levels will reduce the slew rate of the edges and effectively in-
crease the jitter of the signal. ECL terminations for the EN-
CODE and ENCODE signals should be as close as possible to
the AD9060 package to avoid reflections.
In systems where only single-ended signals are available, the use
of a high speed comparator (such as the AD96685) is recom-
mended to convert to differential signals. An alternative is to
connect +1.3 V (ECL midpoint) to ENCODE and drive the
ENCODE connection single ended. In such applications, clean,
fast edges are necessary to minimize jitter in the signal.
Output data of the AD9060, D0–D9 and OVERFLOW are also
ECL compatible and should be terminated through 100 to
–2 V (or an equivalent load).
Data Format
The format of the output data (D0–D9) is controlled by the MSB
INVERT and LSBs INVERT pins. These inputs are dc control
inputs and should be connected to GROUND or +VS. The
AD9060 Truth Table gives information to choose from among
Binary, Inverted Binary, Twos Complement and Inverted Twos
Complement coding.
The OVERFLOW output is an indication that the analog input
signal has exceeded the voltage at +VSENSE. The accuracy of the
overflow transition voltage and output delay are not tested or in-
cluded in the data sheet limits. Performance of the overflow in-
dicator is dependent on circuit layout and slew rate of the en-
code signal. The operation of this function does not affect the
other data bits (D0–D9). It is not recommended for applications
requiring a critical measure of analog input voltage.
Layout and Power Supplies
Proper layout of high speed circuits is always critical but is par-
ticularly important when both analog and digital signals are
involved.
Analog signal paths should be kept as short as possible and be
properly terminated to avoid reflections. The analog input volt-
age and the voltage references should be kept away from digital
signal paths; this reduces the amount of digital switching noise
that is capacitively coupled into the analog section of the circuit.
Digital signal paths should also be kept short, and run lengths
should be matched to avoid propagation delay mismatch. Ter-
minations for ECL signals should be as close as possible to the
receiving gate.
In high speed circuits, layout of the ground circuit is a critical
factor. A single, low impedance ground plane on the component
side of the board will reduce noise on the circuit ground. Power
supplies should be capacitively coupled to the ground plane to
reduce noise in the circuit. Multilayer boards allow designers to
lay out signal traces, without interrupting the ground plane, and
provide low impedance power planes.
It is especially important to maintain the continuity of the
ground plane under and around the AD9060. In systems with
dedicated digital and analog grounds, all grounds of the
AD9060 should be connected to the analog ground plane.
The power supplies (+VS and –VS) of the AD9060 should be
isolated from the supplies used for external devices; this further
reduces the amount of noise coupled into the A/D converter.
Sockets limit the dynamic performance and should be used only
for prototypes or evaluation—PCK Elastomerics Part No. CCS6855
is recommended for the LCC package. (Tel. 215-672-0787)
An evaluation board is available to aid designers and provide a
suggested layout.
–10–
REV. A
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