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ML2252BCP View Datasheet(PDF) - Micro Linear Corporation

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ML2252BCP Datasheet PDF : 13 Pages
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ML2252, ML2259
Another advantage of the capacitor array approach used in
the ML2252 and ML2259 is the inherent sample-and-hold
function. This true S/H allows an accurate conversion to be
done on the input even if the analog signal is not stable.
Linearity and accuracy are maintained for analog signals up
to 1/2 the sampling frequency. As a result, input signals up
to 50kHz can be converted without degradation in linearity
or accuracy.
The sequence of events during a conversion is shown in
figure 5. The rising edge of a START pulse resets the internal
registers and initiates a conversion on the next rising edge
of CLK providing that (tSS) start pulse setup time is satisfied.
If this setup time is not met, start conversion will have an
uncertainty of one clock pulse. The input is then sampled for
the next half CLK period until EOC goes low. EOC goes low
on the falling edge of the next CLK pulse indicating that the
conversion is now beginning. The actual conversion now
takes place for the next eight CLK pulses, one bit for each
CLK pulse. After the conversion is done, the data is updated
on DB0–DB7 and EOC goes high on the rising edge of the
9th CLK pulse, indicating that the conversion has been
completed and data is valid on DB0–DB7. The data will
stay valid on DB0–DB7 until the next conversion updates
the data word on the next rising edge of EOC.
A conversion can be interrupted and restarted at any time
by a new START pulse.
1.3 ANALOG INPUTS AND SAMPLE/HOLD
The ML2252 and ML2259 have a true sample-and-hold
circuit which samples both the selected input and ground
simultaneously. These analog to digital converters can
reject AC common mode signals from DC–50kHz as well
as maintain linearity for signals from DC–50kHz.
The plot in Figure 6 shows a 2048 point FFT of the
ML2259 converting a 50kHz, 0 to 5V, low distortion sine
wave input. The ML2252 and ML2259 sample and
digitize, at their specified accuracy, dynamic input
signals with frequency components up to the Nyquist
frequency (one-half the sampling rate). The output spectra
yields precise measurements of input signal level, harmonic
components, and signal to noise ratio up to the 8-bit level.
The near ideal signal to noise ratio is maintained
independent of increasing analog input frequencies to
50kHz.
The signal at the analog input is sampled during the
interval when the sampling switch is open prior to
conversion start. The sampling window (S/H acquisition
time) is one half CLK period long and occurs one half CLK
period after START goes low. When the sampling switch
closes at the start of the S/H acquisition time, 8pF of
capacitance is thrown onto the analog input. One half
CLK period later, the sampling switch opens, the signal
present at analog input is stored and conversion starts.
Since any error on the analog input at the end of the S/H
acquisition time will cause additional conversion error,
care should be taken to insure adequate settling and
charging time from the source. If more charging or
settling time is needed to reduce these analog input
errors, a longer CLK period can be used.
Each analog input has dual diodes to the supply rails, and
a minimum of ±25mA (±100mA typically) can be
injected into each analog input without causing latchup.
CLK
START
1/fCLK
1
2
3
4
5
6
7
8
9
tSS
tWS
ALE
tWALE
ADDR0–ADDR2
tS
tH
tEOC
EOC
DB0–DB7
OE
tC
PREVIOUS DATA
DATA
tIH, tOH
tHI, tHO
Figure 5. Timing Diagram
8
 

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