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ML2252 View Datasheet(PDF) - Micro Linear Corporation

Part NameDescriptionManufacturer
ML2252 P Compatible 8-Bit A/D Converters with 2- or 8-Channel Multiplexer Micro-Linear
Micro Linear Corporation Micro-Linear
ML2252 Datasheet PDF : 13 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ML2252, ML2259
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
AC and Dynamic Performance Characteristics (Note 5)
tACQ
Sample and Hold Acquisition
fCLK
Clock Frequency
10
tC
Conversion Time
SNR
Signal to Noise Ratio
VIN = 51kHz, 5V sine.
fCLK = 1.46MHz
(fSAMPLING > 150kHz). Noise is sum
of all nonfundamental components
up to 1/2 of fSAMPLING
THD
Total Harmonic Distortion
VIN = 51kHz, 5V sine.
fCLK = 1.46MHz
(fSAMPLING > 150kHz).
THD is sum 2, 3, 4, 5 harmonics
relative to fundamental
1/2
1/fCLK
1460
kHz
8.5 8.5 + 250ns 1/fCLK
47
dB
–60
dB
IMD
Intermodulation Distortion
VIN = fA + fB. fA = 49kHz, 2.5V sine.
–60
dB
fB = 47.8kHz, 2.5V sine,
fCLK = 1.46MHz
(fSAMPLING > 150kHz). IMD is (fA + fB),
(fA – fB), (2fA + fB), (2fA – fB), (fA + 2fB),
(fA – 2fB) relative to fundamental
FR
Frequency Response
VIN = 0 to 50kHz. 5V sine relative
0.1
dB
to 1kHz
tDC
tEOC
tWS
tSS
tWALE
Clock Duty Cycle
End of Conversion Delay
Start Pulse Width
Start Pulse Setup Time
Address Latch Enable
Pulse Width
(Note 6)
Synchronous only, (Note 7)
40
60
%
1/2 1/2 + 250ns 1/fCLK
50
ns
40
ns
50
ns
tS
tH
tH1, H0
t1H, 0H
CIN
COUT
Address Setup
Address Hold
Output Enable for DB0–DB7
Output Disable for DB0–DB7
Capacitance of Logic Input
Capacitance of Logic Outputs
Figure 1, CL = 50pF
Figure 1, CL = 10pF
Figure 1, CL = 50pF
Figure 1, CL = 10pF
0
ns
50
ns
100
ns
50
ns
100
ns
50
ns
5
pF
10
pF
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Total unadjusted error includes offset, full scale, linearity, multiplexer and sample and hold errors.
For –VREF • VIN (+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages
one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can
cause this input diode to conduct — especially at elevated temperatures, and cause errors for analog inputs near full scale. The spec allow 100mV forward bias of either
diode. This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 100mV, the output code will be correct. To achieve an
absolute 0VDC to 5VDC input voltage range will therefore require a minimum supply voltage of 4.900VDC over temperature variations, initial tolerance and loading.
Leakage current is measured with the clock not switching.
CL = 50pF, timing measured at 50% point.
A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits,
the minimum time the clock is high or the minimum time the clock is low must be at least 40ns. The maximum time the clock can be high or low is 60µs.
The conversion start setup time requirement only needs to be satisfied if a conversion must be synchronized to a given clock rising edge. If the setup time is not met,
start conversion will have an uncertainty of one clock pulse.
5
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