AD7575 View Datasheet(PDF) - Analog Devices
Part Name
Description
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AD7575 Datasheet PDF : 12 Pages
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AD7575–SPECIFICATIONS (VDD = +5 V, VREF = +1.23 V, AGND = DGND = 0 V; fCLK = 4 MHz external;
all specifications TMIN to TMAX unless otherwise noted)
Parameter
J, A Versions1 K, B Versions S Version T Version Units
Conditions/Comments
ACCURACY
Resolution
Total Unadjusted Error
Relative Accuracy
Minimum Resolution for Which
No Missing Codes Is Guaranteed
Full-Scale Error
+25°C
TMIN to TMAX
Offset Error2
+25°C
TMIN to TMAX
ANALOG INPUT
Voltage Range
DC Input Impedance
Slew Rate, Tracking
SNR3
8
±2
±1
8
±1
±1
± 1/2
± 1/2
0 to 2 VREF
10
0.386
45
REFERENCE INPUT
VREF (For Specified Performance)
1.23
IREF
500
LOGIC INPUTS
CS, RD
VINL, Input Low Voltage
0.8
VINH, Input High Voltage
2.4
IIN, Input Current
+25°C
±1
TMIN to TMAX
± 10
CIN, Input Capacitance3
10
CLK
VlNL, Input Low Voltage
0.8
VINH, Input High Voltage
2.4
IINL, Input Low Current
700
IINH, Input High Current
700
LOGIC OUTPUTS
BUSY, DB0 to DB7
VOL, Output Low Voltage
0.4
VOH, Output High Voltage
4.0
DB0 to DB7
Floating State Leakage Current
±1
Floating State Output Capacitance3 10
8
±1
± 1/2
8
±1
±1
± 1/2
± 1/2
0 to 2 VREF
10
0.386
45
1.23
500
0.8
2.4
±1
± 10
10
0.8
2.4
700
700
0.4
4.0
±1
10
8
8
±2
±1
±1
± 1/2
8
8
±1
±1
±1
±1
± 1/2
± 1/2
± 1/2
± 1/2
Bits
LSB max
LSB max
Bits max
LSB max Full-Scale TC Is Typically 5 ppm/°C
LSB max
LSB max Offset TC Is Typically 5 ppm/°C
LSB max
0 to 2 VREF 0 to 2 VREF
10
10
0.386
0.386
45
45
Volts
MΩ min
V/µs max
dB min
1 LSB = 2 VREF/256; See Figure 16
VIN = 2.46 V p-p @ 10 kHz; See Figure 11
1.23
1.23
500
500
Volts
µA max
± 5%
0.8
0.8
2.4
2.4
±1
±1
± 10
± 10
10
10
0.8
0.8
2.4
2.4
800
800
800
800
V max
V min
µA max
µA max
pF max
VIN = 0 or VDD
VIN = 0 or VDD
V max
V min
µA max
µA max
VINL = 0 V
VINH = VDD
0.4
0.4
4.0
4.0
± 10
± 10
10
10
V max
V min
µA max
pF max
ISINK = 1.6 mA
ISOURCE = 40 µA
VOUT = 0 to VDD
CONVERSION TIME4
With External Clock
5
5
With Internal Clock, TA = +25°C
5
5
15
15
5
5
5
5
15
15
POWER REQUIREMENTS5
VDD
IDD
Power Dissipation
Power Supply Rejection
+5
+5
6
6
15
15
± 1/4
± 1/4
+5
+5
7
7
15
15
± 1/4
± 1/4
NOTES
1Temperature ranges are as follows:
J, K Versions; 0°C to +70°C
A, B Versions; –25°C to +85°C
S, T Versions; –55°C to +125°C
2Offset error is measured with respect to an ideal first code transition that occurs at 1/2 LSB.
3Sample tested at +25°C to ensure compliance.
4Accuracy may degrade at conversion times other than those specified.
5Power supply current is measured when AD7575 is inactive i.e., when CS = RD = BUSY = logic HIGH.
Specifications subject to change without notice.
µs
µs min
µs max
Volts
mA max
mW typ
LSB max
fCLK = 4 MHz
Using Recommended Clock
Components Shown in Figure 15
± 5% for Specified Performance
Typically 3 mA with VDD = +5 V
4.75 V ≤ VDD ≤ 5.25 V
–2–
REV. B
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