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D006 View Datasheet(PDF) - California Micro Devices => Onsemi

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D006
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California Micro Devices => Onsemi CMD
D006 Datasheet PDF : 6 Pages
1 2 3 4 5 6
CALIFORNIA MICRO DEVICES
PAC DN006
Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to increased
negative voltage on the line being protected.
Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies exhibit
a much higher output impedance to fast transient current spikes. In the VZ equation above, the VSupply term, in reality, is
given by (VDC + Iesd x Rout), where VDC and Rout are the nominal supply DC output voltage and effective output impedance
of the power supply respectively. As an example, a Rout of 1 ohm would result in a 10V increment in VZ for a peak Iesd of
10A. To mitigate this effect, a high frequency bypass capacitor should be connected between the VP pin of the PAC DN006
and the ground plane. The value of this bypass capacitor should be chosen such that it will absorb the charge transferred
by the ESD pulse with minimal change in Vp. Typically a value in the 0.1 µF to 0.2 µF range is adequate for IEC-1000-4-2,
level 4 contact discharge protection (8KV). Ceramic chip capacitors mounted with short printed circuit board traces are a
good choice for this application. Electrolytic capacitors should be avoided as they have poor high frequency characteristics.
For extra protection, connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series
inductance inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher than the
maximum supply voltage.
As a general rule, the PAC DN006 should be located as close as possible to the point of entry of expected electrostatic
discharges. The power supply bypass capacitor mentioned above should be as close to the PAC DN006 as possible, with
minimum PCB trace lengths to the power supply and ground planes to minimize stray series inductance.
Implementation Examples
ESD events are very high speed pulses with rise times in the range of 1 nS or less. To effectively use the PAC DN006, the
following design guidelines must be observed (as discussed in the application section):
1. The inductance from the VN and VP connections of the PAC DN006 to ground must be very low. This includes the path
through the VP decoupling capacitor to ground and the path to the power supply (as discussed above).
2. The inductance between the connector pin to be protected and the PAC DN006 channel input pin must be kept to a
minimum. (If there is a large inductance here, the ESD event will find a lower impedance path which will more likely be
through the device to be protected.) Figure 2 shows the implementation schematic and Figure 3 shows a possible layout
for the PAC DN006. In Figure 3, notice the large VCC and ground areas with multiple via connections to the underlying
reference planes and the positioning of the bypass capacitor. Note how the signal lines to be protected flow from the
connector to the PAC DN006 and then out to the device to be protected (Figures 3, 4, and 5). This daisy chaining
provides a low impedance path from the connector to the PAC DN006 and a higher impedance path from the PAC DN006
to the protected device.
POSITIVE SUPPLY RAIL
CHANNEL
INPUT
D1
ONE
D2
CHANNEL
OF
PAC DN006
DECOUPLING
CAPACITOR
0.1uF
LINE BEING
PROTECTED
OPTIONAL
ZENER DIODE
FOR EXTRA
PROTECTION
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
GROUND RAIL
POWER
SUPPLY
Figure 2
© 1999 Calirornia Micro Devices Corp. All rights reserved.
3/99 Rev 1
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
3
 

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