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HC05J5AGRSH View Datasheet(PDF) - Freescale Semiconductor

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HC05J5AGRSH
Freescale
Freescale Semiconductor Freescale
HC05J5AGRSH Datasheet PDF : 106 Pages
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Freescale Semiconductor, Inc.
July 16, 1999
GENERAL RELEASE SPECIFICATION
4.3 SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction and a non-maskable interrupt since it is exe-
cuted regardless of the state of the I-bit in the CCR. As with any instruction, inter-
rupts pending during the previous instruction will be serviced before the SWI
opcode is fetched. The interrupt service routine address is speciļ¬ed by the con-
tents of memory locations $0FFC and $0FFD.
4.4 HARDWARE INTERRUPTS
All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the
I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing
the I-bit enables the hardware interrupts. There are two types of hardware inter-
rupts which are explained in the following sections.
4.5 EXTERNAL INTERRUPT (IRQ)
The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of
the IRQ function is shown in Figure 4-2.
IRQ Pin
PA0
PA1
PA2
PA3
Mask Option
(Port A External Int.)
RST
IRQR
Mask Option
(IRQ Level)
IRQ Fetch Vector
IRQE1
IRQE
IRQE1
VDD
IRQ
LATCH
R
to BIH & BIL
instruction
sensing
IRQF
to IRQ
processing
in CPU
PA7
RST
IRQR1
VDD
IRQ1
LATCH
R
Figure 4-2. IRQ Function Block Diagram
IRQF1
INTERRUPTS
REV 2.1
4-3
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