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MC68HC05J3 View Datasheet(PDF) - Motorola => Freescale

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MC68HC05J3 Datasheet PDF : 92 Pages
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to the value in the core timer counter register/RTI divider, hence the actual COP timeout period
will vary between 7x and 8x the RTI period.
The COP function is a mask option, enabled or disabled during device manufacture.
If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched.
COP timeout is prevented by writing a ‘0’ to bit 0 of address $0FF0. When the COP is cleared, only
the final divide-by-eight stage is cleared (see Figure 5-1).
5.3
Core timer registers
5
5.3.1 Core timer control and status register (CTCSR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Core timer control/status (CTCSR) $0008 CTOF RTIF CTOFE RTIE 0
0 RT1 RT0 uu00 0011
CTOF — Core timer overflow
1 (set) – Core timer overflow has occurred.
0 (clear) – No core timer overflow interrupt has been generated.
This bit is set when the core timer counter register rolls over from $FF to $00; an interrupt request
will be generated if CTOFE is set. When set, the bit may be cleared by writing a ‘0’ to it.
RTIF — Real time interrupt flag
1 (set) – A real time interrupt has occurred.
0 (clear) – No real time interrupt has been generated.
This bit is set when the output of the chosen stage becomes active; an interrupt request will be
generated if RTIE is set. When set, the bit may be cleared by writing a ‘0’ to it.
CTOFE — Core timer overflow enable
1 (set) – Core timer overflow interrupt is enabled.
0 (clear) – Core timer overflow interrupt is disabled.
Setting this bit enables the core timer overflow interrupt. A CPU interrupt request will then be
generated whenever the CTOF bit becomes set. Clearing this bit disables the core timer overflow
interrupt capability.
MC68HC05J3
CORE TIMER
TPG
MOTOROLA
5-3
 

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