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MC68HC05J3 View Datasheet(PDF) - Motorola => Freescale

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MC68HC05J3 Datasheet PDF : 92 Pages
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Reset does not affect the state of the data register, but clears the data direction register, thereby
returning all port pins to input mode. Writing a ‘1’ to any DDR bit sets the corresponding port pin
to output mode.
Provided that the interrupt mask bit of the condition code register is cleared, the keyboard interrupt
facility is enabled by setting the keyboard interrupt enable bit (KIE) in the port B configuration
register at location $07. The configuration register is described in Section 4.4.3.
Pins configured as output do not contribute to the wired-or interrupt. The structure of the port pins
is shown diagrammatically in Figure 4-2. When a low-to-high transition is detected on any of these
port pins, a keyboard interrupt request is generated and the port B interrupt status flag (KSF) is
4
set. The address of the interrupt service routine is specified by the contents of memory locations
$0FFA and $0FFB. Since this interrupt vector is shared with the IRQ external interrupt function,
the interrupt service routine should check KSF to determine the interrupt source. KSF can be
cleared by accessing the port B data register. The keyboard interrupt is edge sensitive. Care must
be taken to allow adequate time for switch debounce before clearing the flag.
A keyboard interrupt will force the MCU out of STOP or WAIT mode.
IRQ
PB3
DDRB3
PB2
DDRB2
PB1
DDRB1
PB0
DDRB0
KIE
+
+
+
&
&
&
Edge
detect Internal
interrupt
+
Figure 4-2 Port B keyboard interrupt function
MC68HC05J3
INPUT/OUTPUT PORTS
TPG
MOTOROLA
4-3
 

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