56F8037/56F8027 Signal Pins
Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued)
Signal LQFP
Name Pin No.
Type
State During
Reset
Signal Description
GPIOA13 44
(MISO1)
(TB210)
(TA211)
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input,
internal
pull-up
enabled
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
QSPI1 Master In/Slave Out— This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device
is not selected. The slave device places data on the MISO line a
half-cycle before the clock edge the master devices uses to latch the
data.
TB2 — Timer B, Channel 2.
TA2 — Timer A, Channel 2.
After reset, the default state is GPIOA13. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
10The TB2 signal is also brought out on the GPIOA10 pin.
11The TA2 signal is also brought out on the GPIOA4, GPIOA8 and GPIOB2 pins.
GPIOA14 45
(MOSI1)
Input/
Output
Input/
Output
Input,
internal
pull-up
enabled
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
QSPI1 MasterOut/Slave In — This serial data pin is an output from
a master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge the
slave devices uses to latch the data.
TB3 — Timer B, Channel 3.
(TB312)
Input/
Output
TA3 — Timer A, Channel 3.
(TA313)
Input/
Output
After reset, the default state is GPIOA14. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
12The TB3 signal is also brought out on the GPIOA11 pin.
13The TA3 signal is also brought out on the GPIOA5, GPIOA9, and GPIOB3 pins.
Return to Table 2-2
56F8037/56F8027 Data Sheet, Rev. 6
Freescale Semiconductor
29