MC33793DR2 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
View to exact match
MC33793DR2 Datasheet PDF : 24 Pages
| |||
Freescale Semiconductor, Inc.
when a value is being captured by the controller, the controller
will signal that an invalid A/D value was obtained.
The value of “0" (binary 00000000) is reserved by the control
logic to signal an error. A value of "0" from the ADC will be
reported as "1" (binary 00000001) by the control logic.
Serial Encoder
The Serial Encoder accepts the digitized value from the ADC
and formatting/data from the Control Logic. A logic transition
from Idle to Signal High and then to Signal Low at BUSIN will
cause the first bit to be presented to the current switch
(Response Loading). A transition to Signal High and back to
Signal Low will cause the next bit to be presented to the current
switch. This will continue until a transition back to Idle turns off
the current switch.
Slew
The slew circuit serves to reduce EMI produced as a result
of switching the bus loading current sink element. The slew
circuit limits the rise and fall time of current loading the bus by
controlling the current sinking element.
Switched Current Source
A "1" data return bit will be signaled by turning on a fixed
current source. During signaling time, the 33793 will be using
power from H_CAP and not loading the bus for power. The
current will be drawn from either BUSIN or BUSOUT or split
between them. The split can be in any proportion as long as the
total is correct.
The current source is turned off whenever the bus is at Idle
level.
Level Detector
The level detector contains comparators to determine if the
BUSIN or BUSOUT is at idle, logic high, or logic low. The inputs
from BUSIN and BUSOUT are sensed by the device so that if
either side is driven by the signaling waveform while the other
is not, the signaling will be detected. This circuit also provides a
signal to indicate if the signal is being received on the BUSOUT
pin. If a "reverse initialization" command is received, it can only
be acted upon if the device is not already initialized and if the
signal is present on BUSOUT.
Serial Decoder
The Serial Decoder monitors transitions on the BUSIN or
BUSOUT. When the 33793 is Idle and supplying power to itself
and the external device(s) (via REGOUT), the input to BUSIN
will be in the Idle state. A transition from this level to Signal Low
(through Signal High) will start the process of decoding a word
of data. BUSIN is driven from Signal Low to Signal High for each
bit and back to Signal Low to start the next bit. The
determination of whether the bit was a one or a zero is made by
determining whether it spent more time low (a zero) or high (a
one). The end of the word is signaled by a transition at the end
of the last bit from Signal High to Idle. The advantage of this
method is that it will accept data over a wide range of rates and
is not dependent on an accurate clock.
The controller will typically indicate a logic zero by spending
2/3 of the bit period at Signal Low and 1/3 at Signal High. A logic
one would be 1/3 of the bit period at Signal Low and 2/3 at
Signal High.
Control Logic
The control logic performs the digital operations carried out
by this device. Its principle functions include:
• Decoding input instructions.
• Control the general purpose I/O and LOGICOUT in
response to BUSIN or BUSOUT commands.
• Control A/D conversions.
• Form response word.
• Capture and store address.
• Control BUSSW.
• Reset device on power-up.
• Control the general purpose I/O logic configuration.
• Read the general purpose I/O logic values and respond to
request for these values.
• Generating a cycle redundancy check (CRC) for the
received data and transmitted data in conformance with
the DSI Bus Standard.
Additionally, the control logic performs error checking on the
received data. If errors are found, no action is taken and no
response is made. Errors include:
• CRC received doesn’t match CRC of received data.
• Number of received bits is not 12 or 20.
Clock
The clock is a low-stability type with the capacitor integrated
onto the die. The signaling system and all internal operations
are such that no external precision timing device is needed in
the normal operation of this device.
Bus Switch (BUSSW)
The bus switch passes signaling and power to all
subsequent devices on the bus. It can block a voltage of either
polarity up to the highest idle state level between BUSIN and
BUSOUT.
LOGICOUT
LOGICOUT is a logic level output with enhanced high-side
drive capability.
Addressing
The 33793 IC supports both runtime programmable and pre-
programmed addressing as defined in the DSI Specification.
Runtime programmable addressing uses the daisy chain bus
connection. Pre-programmed devices may either be connected
in daisy chain or in parallel on the bus wires.
33793
10
For More Information OMnOTTOhRiOsLAPrAoNdAuLOcGt,INTEGRATED CIRCUIT DEVICE DATA
Go to: www.freescale.com
|
|
Share Link: 