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MC33023DWR2 View Datasheet(PDF) - ON Semiconductor

Part NameDescriptionManufacturer
MC33023DWR2 High Speed Single−Ended PWM Controller ON-Semiconductor
ON Semiconductor ON-Semiconductor
MC33023DWR2 Datasheet PDF : 18 Pages
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MC34023, MC33023
OPERATING DESCRIPTION
The MC33023 and MC34023 series are high speed, fixed
frequency, single−ended pulse width modulator controllers
optimized for high frequency operation. They are
specifically designed for Off−Line and DC−to−DC
converter applications offering the designer a cost effective
solution with minimal external components. A
representative block diagram is shown in Figure 19.
Oscillator
The oscillator frequency is programmed by the values
selected for the timing components RT and CT. The RT pin
is set to a temperature compensated 3.0 V. By selecting the
value of RT, the charge current is set through a current mirror
for the timing capacitor CT. This charge current runs
continuously through CT. The discharge current is ratioed to
be 10 times the charge current, which yields the maximum
duty cycle of 90%. CT is charged to 2.8 V and discharged to
1.0 V. During the discharge of CT, the oscillator generates an
internal blanking pulse that resets the PWM Latch and,
inhibits the outputs. The threshold voltage on the oscillator
comparator is trimmed to guarantee an oscillator accuracy
of 5.0% at 25°C.
Additional dead time can be added by externally
increasing the charge current to CT as shown in Figure 24.
This changes the charge to discharge ratio of CT which is set
internally to Icharge/10 Icharge. The new charge to discharge
ratio will be:
% Deadtime +
Iadditional ) Icharge
10 (Icharge)
A bidirectional clock pin is provided for synchronization
or for master/slave operation. As a master, the clock pin
provides a positive output pulse during the discharge of CT.
As a slave, the clock pin is an input that resets the PWM latch
and blanks the drive output, but does not discharge CT.
Therefore, the oscillator is not synchronized by driving the
clock pin alone. Figures 28, 29 and 30 provide suggested
synchronization.
Error Amplifier
A fully compensated Error Amplifier is provided. It
features a typical DC voltage gain of 95 dB and a gain
bandwidth product of 8.3 MHz with 75 degrees of phase
margin (Figure 4). Typical application circuits will have the
noninverting input tied to the reference. The inverting input
will typically be connected to a feedback voltage generated
from the output of the switching power supply. Both inputs
have a common mode voltage (VCM) input range of 1.5 V to
5.5 V. The Error Amplifier Output is provided for external
loop compensation.
Soft−Start Latch
Soft−Start is accomplished in conjunction with an
external capacitor. The Soft−Start capacitor is charged by an
internal 9.0 mA current source. This capacitor clamps the
output of the error amplifier to less than its normal output
voltage, thus limiting the duty cycle. The time it takes for a
capacitor to reach full charge is given by:
t [ (4.5 105) CSoft-Start
A Soft−Start latch is incorporated to prevent erratic
operation of this circuitry. Two conditions can cause the
Soft−Start circuit to latch so that the Soft−Start capacitor
stays discharged. The first condition is activation of an
undervoltage lockout of either VCC or Vref. The second
condition is when current sense input exceeds 1.4 V. Since
this latch is “set dominant”, it cannot be reset until either of
these signals is removed and, the voltage at CSoft−Start is less
than 0.5 V.
PWM Comparator and Latch
A PWM circuit typically compares an error voltage with
a ramp signal. The outcome of this comparison determines
the state of the output. In voltage mode operation the ramp
signal is the voltage ramp of the timing capacitor. In current
mode operation the ramp signal is the voltage ramp induced
in a current sensing element. The ramp input of the PWM
comparator is pinned out so that the user can decide which
mode of operation best suits the application requirements.
The ramp input has a 1.25 V offset such that whenever the
voltage at this pin exceeds the error amplifier output voltage
minus 1.25 V, the PWM comparator will cause the PWM
latch to set, disabling the outputs. Once the PWM latch is set,
only a blanking pulse by the oscillator can reset it, thus
initiating the next cycle.
Current Limiting and Shutdown
A pin is provided to perform current limiting and
shutdown operations. Two comparators are connected to the
input of this pin. The reference voltage for the current limit
comparator is not set internally. A pin is provided so the user
can set the voltage. When the voltage at the current limit
input pin exceeds the externally set voltage, the PWM latch
is set, disabling the output. In this way cycle−by−cycle
current limiting is accomplished. If a current limit resistor is
used in series with the power devices, the value of the
resistor is found by:
ILimit Reference Voltage
RSense +
Ipk (switch)
If the voltage at this pin exceeds 1.4 V, the second
comparator is activated. This comparator sets a latch which,
in turn, causes the soft start capacitor to be discharged. In this
way a “hiccup” mode of recovery is possible in the case of
output short circuits. If a current limit resistor is used in
series with the output devices, the peak current at which the
controller will enter a “hiccup” mode is given by:
Ishutdown +
1.4 V
RSense
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