ÎÎÎÎSÎÎÎÎWIÎÎÎÎTCHÎÎÎÎINGÎÎÎÎCHÎÎÎÎARÎÎÎÎAChCaÎÎÎÎTrEacRtÎÎÎÎeISriTsÎÎÎÎtIiCcSÎÎÎÎ* (CÎÎÎÎL=5ÎÎÎÎ0pFÎÎÎÎ,TAÎÎÎÎ=2ÎÎÎÎ5_CÎÎÎÎ)SymÎÎÎÎbolÎÎÎÎÎÎÎÎVÎÎÎÎDDÎÎÎÎÎÎÎÎÎÎÎÎMinÎÎÎÎÎÎÎÎTÎÎÎÎypÎÎÎÎ# ÎÎÎÎÎÎÎÎMaxÎÎÎÎÎÎÎÎUÎÎÎÎnitÎÎÎÎ
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
ns
tTHL
5.0
—
100
200
10
—
50
100
15
—
40
80
Propagation Delay Time
tPLH, tPHL = (1.7 ns/pF) CL + 165 ns
tPLH, tPHL = (0.66 ns/pF) CL + 82
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns
tPLH,
ns
tPHL
5.0
—
250
500
10
—
115
225
15
—
90
165
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
+VDD
PULSE
Vin
GENERATOR
VDD
A
Z0
B
X0
Y0
Z1
X1
Y1
X2
Z2
Y2
X3
Y3
Z3
VSS
CL
20 ns
20 ns
CL
90%
VDD
Vin
10%
VSS
50% DUTY CYCLE
CL
CL
ISS
500 µF
PULSE
GENERATOR
Figure 1. Dynamic Power Dissipation Test Circuit and Waveform
VDD
A VDD Z0
B
X0
Y0 Z1
X1
Y1
X2 Z2
Y2
X3
Y3 VSS Z3
CL
CL
OUTPUTS
CL
CL
20 ns
INPUT
tPHL
OUTPUT
tPLH
OUTPUT
90%
50%
10%
90%
50%
10%
tTHL
50%
Figure 2. Switching Time Test Circuit and Waveforms
20 ns
VDD
VSS
tPLH
VOH
VOL
tTLH
tPHL VOH
VOL
MOTOROLA CMOS LOGIC DATA
MC14519B
3