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MC145181 View Datasheet(PDF) - Motorola => Freescale

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MC145181 Datasheet PDF : 71 Pages
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Freescale SMeCm14i5c1o8n1 ductor, Inc.
4. DEVICE OVERVIEW
Reference Counter for Main Loop
Refer to the Block Diagram in Section 1.
4A. SERIAL INTERFACE AND REGISTERS
The serial interface is comprised of a Clock pin (Clk), a
Data In pin (Din), and an Enable pin (Enb). Information on the
data input pin is shifted into a shift register on the low–to–high
transition of the serial clock. The data format is most
significant bit (MSB) first. Both Clk and Enb are
Schmitt–triggered inputs.
The R and N registers contain counter divide ratios for the
main loop, PLL. The Ri and Ni registers contain counter
divide ratios for the secondary loop, PLLi. Additional contol
bits are located in the Ri, N, and C registers. The D register
controls the digital–to–analog converters (DACs). Random
access is allowed to the N, Ri, Hr, Hni, D, and C registers.
Two 16–bit holding registers, Hr and Hni, feed registers R
and Ni, respectively. [The three least significant bits (LSBs)
of the Hni register are not used.] The R and Ni registers
determine the divide ratios of the R and Ni counters,
respectively. Thus, the information presented to the R and Ni
counters is double–buffered. Using the proper programming
sequence, new divide ratios may be presented to the N, R,
and Ni counters; simultaneously.
Enb is used to activate the data port and allow transfer of
data. To ensure that data is accepted by the device, the Enb
signal line must initially be a high voltage (not asserted), then
make a transition to a low voltage (asserted) prior to the
occurrence of a serial clock, and must remain asserted until
after the last serial clock of the burst. Serial data may be
transferred in an SPI format (while Enb remains asserted).
Data is transferred to the appropriate register on the rising
edge of Enb (see Table 1). “Short shifting”, depicted as
BitGrabberin the table, allows access to certain registers
without requiring address bits. When Enb is inactive (high),
Clk is inhibited from shifting the shift register.
The serial input pins may NOT be driven above the supply
voltage applied to the Vpos pins.
4B. REFERENCE INPUT AND COUNTERS CIRCUITS
Reference (Oscillator) Circuit
For the Colpitts reference oscillator, one pin ties to the
base (Oscb, pin 32) and the other ties to the emitter (Osce,
pin 1), of an on–chip NPN transistor. In addition, the
reference circuit may be operated in the external reference
(XRef) mode as selectable via bit C6 when the Mode pin is
high.
The Oscb and Osce pins support an external fundamental
or overtone crystal. The output of the oscillator is routed to
both the reference counter for the main loop (R counter) and
the reference counter for the secondary loop (Ri counter).
In a second mode, determined by bit C6 being 1 and the
Mode pin being high, Osce is an input which accepts an
ac–coupled signal from a TCXO or other source. Oscb must
be floated. If the Mode pin is low, this “XRef mode” is not
allowed.
Main reference counter R divides down the frequency at
Osce and feeds the phase/frequency detector for the main
loop. The detector feeds the two charge pumps with outputs
PDout–Hi and PDout–Lo. The division ratio of the R counter is
determined by bits in the R register.
Reference Counter for Secondary Loop
Secondary reference counter Ri divides down the
frequency at Osce and feeds the phase/frequency detector
for the secondary loop. The detector output is PDouti. The
division ratio of the Ri counter is determined by the 16 LSBs
of the Ri register.
The Ri counter has a special mode to provide a frequency
output at pins fout and fout (differential outputs). These are
low–jitter ECL–type outputs. With the Mode pin low, software
control allows the Osce frequency to be divided–by–8, –10,
or –12.5 and routed to the fout pins. This output is derived by
tapping off of a front–end stage of the Ri counter and feeding
the auxiliary counter which provides the divided–down
frequency. The chip must have the Mode pin low, which
activates the fout pins. The actual Ri divide ratio must be
divisible by 2 or 2.5 when the fout pins are activated. There is
no such restriction when the Mode pin is high. See
Section 6D, Ri Register.
4C. LOOP DIVIDER INPUTS AND COUNTER CIRCUITS
fin Inputs and Counter Circuit
fin and fin are high–frequency inputs to the amplifier which
feeds the N counter. A small signal can feed these inputs
either differentially or single–ended.
The N counter divides down the external VCO frequency
for the main loop. (The divide ratio of the N counter is also
known as the loop multiplying factor.) The divide ratio of this
counter is determined by the 18 LSBs of the N register. The
output of the N counter feeds the phase/frequency detector
for the main loop.
fini Input and Counter Circuit
fini is the high–frequency input to the amplifier which feeds
the N i counter. A small signal can feed this input
single–ended.
The Ni counter divides down the external VCO frequency
for the secondary loop. (The divide ratio of the Ni counter is
also known as the loop multiplying factor.) The divide ratio of
this counter is determined by bits in the Ni register. The
output of the Ni counter feeds the phase/frequency detector
for the secondary loop.
4D. VOLTAGE MULTIPLIER AND KEEP–ALIVE
CIRCUITS
The voltage multiplier produces approximately two times
the voltage present at the Vpos pins over a supply range of
1.8 V to about 2.5 V. With a supply range of approximately
2.5 V to 3.6 V, the elevated voltage is regulated/limited to
approximately 5 V. The elevated voltage, present at the Cmult
MOTOROLA RF/IF DEVICE DATA For More Information On This Product,
9
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