MC145162 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

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MC145162

60 MHz and 85 MHz Universal Programmable Dual PLL Frequency Synthesizers

Motorola => Freescale 

PIN DESCRIPTIONS

INPUT PINS

OSCin /OSCout

Reference Oscillator Input/Output (Pins 7, 8)

These pins form a reference oscillator when connected to

an external parallel–resonant crystal. Figure 6 shows the

relationship of different crystal frequencies and reference

frequencies for cordless phone applications in various coun-

tries. OSCin may also serve as input for an externally gen-

erated reference signal which is typically ac coupled.

MCUCLK

System Clock (Pin 5)

This output pin provides a signal of the crystal frequency

(OSCout) divided by 3 or 4 that is controlled by a bit in the

control register.

This signal can be a clock source for the MCU or other sys-

tem clocks.

ADin, Din, CLK, ENB

Auxiliary Data In, Data In, Clock, Enable (Pins 2, 3, 1, 4)

These four pins provide an MCU serial interface for pro-

gramming the reference counter, the transmit–channel count-

er, and the receive–channel counter. They also provide

various controls of the PLL including the power saving mode

and the programming format.

TxPS/fTx, RxPS/fRx

Transmit Power Save, Receive Power Save (Pins 13, 11)

For a normal application, these output pins provide the

status of the internal power saving mode operation. If the

transmit–channels counter circuitry is in power down mode,

TxPS/fTx outputs a high state. If the receive–channels

counter circuitry is in power down mode, RxPS/fRx is set high.

These outputs can be applied for controlling the external pow-

er switch for the transmitter and the receiver to save MCU

control pins.

In the Tx/Rx channel counter test mode, the TxPS/fTx and

RxPS/fRx pins output the divided value of the transmit

channel counter (fTx) and the receive channel counter (fRx),

respectively. This test mode operation is controlled by the

control register. Details of the counter test mode are in the Tx/

Rx Channel Counter Test section of this data sheet.

fin–T/fin–R

Transmit/Receive Counter Inputs (Pins 14, 9)

fin–T and fin–R are inputs to the transmit and the receive

counters, respectively. These signals are typically driven from

the loop VCO and ac coupled. The minimum input signal level

is 200 mV p–p @ 60.0 MHz.

OUTPUT PINS

TxPDout/RxPDout

Transmit/Receive Phase Detector Outputs (Pins 15, 10)

These are three–state outputs of the transmit and receive

phase detectors for use as loop error signals (see Figure 7 for

phase detector output waveforms). Phase detector gain is

VDD/4 π volts per radian.

Frequency fV > fR or fV leading: output = negative pulse.

Frequency fV < fR or fV lagging: output = positive pulse.

Frequency fV = fR and phase coincidence: output = high–

impedance state.

NOTE: fR is the divided–down reference frequency at the

phase detector input and fV is the divided–down VCO

frequency at the phase detector input.

LD

Lock Detect (Pin 16)

The lock detect signal is associated with the transmit loop.

The output at a high level indicates an out–of–lock condition

(see Figure 7 for the LD output waveform).

POWER SUPPLY

VDD

Positive Power Supply (Pin 12)

VDD is the most positive power supply potential ranging

from 2.5 to 5.5 V with respect to VSS.

VSS

Negative Power Supply (Pin 6)

VSS is the most negative supply potential and is usually

connected to ground.

OSCin

OSCout

N (12 BITS)

M (14 BITS)

A

fR1

4

B

C

25

D

fR2

Crystal

11.150 MHz

11.150 MHz

10.240 MHz

12.000 MHz

N Value

446

223

512

600

fR1→B

6.25 kHz

12.5 kHz

5.0 kHz

5.0 kHz

fR2→C

1.0 kHz

Figure 6. Reference Frequencies for Cordless Phone Applications of Various Countries

MC145162•MC145162–1

6

MOTOROLA

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