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MC14025BCP View Datasheet(PDF) - ON Semiconductor

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MC14025BCP
ON-Semiconductor
ON Semiconductor ON-Semiconductor
MC14025BCP Datasheet PDF : 14 Pages
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MC14001B Series
BSERIES GATE SWITCHING TIMES
SWITCHING CHARACTERISTICS (5) (CL = 50 pF, TA = 25_C)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic
VDD
Symbol
Vdc
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Rise Time, All BSeries Gates
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTLH = (1.35 ns/pF) CL + 33 ns
tTLH = (0.60 ns/pF) CL + 20 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTLH = (0.40 ns/PF) CL + 20 ns
tTLH
5.0
10
15
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Fall Time, All BSeries Gates
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTHL = (1.35 ns/pF) CL + 33 ns
tTHL = (0.60 ns/pF) CL + 20 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTHL = (0.40 ns/pF) CL + 20 ns
tTHL
5.0
10
15
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Propagation Delay Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MC14001B, MC14011B only
tPLH, tPHL = (0.90 ns/pF) CL + 80 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (0.36 ns/pF) CL + 32 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (0.26 ns/pF) CL + 27 ns
All Other 2, 3, and 4 Input Gates
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (0.90 ns/pF) CL + 115 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (0.36 ns/pF) CL + 47 ns
tPLH, tPHL = (0.26 ns/pF) CL + 37 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 8Input Gates (MC14068B, MC14078B)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (0.90 ns/pF) CL + 155 ns
tPLH, tPHL = (0.36 ns/pF) CL + 62 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (0.26 ns/pF) CL + 47 ns
tPLH, tPHL
5.0
10
15
5.0
10
15
5.0
10
15
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 5. The formulas given are for the typical characteristics only at 25_C.
Min
Typ (6)
Max
Unit
ns
100
200
50
100
40
80
ns
100
200
50
100
40
80
ns
125
250
50
100
40
80
160
300
65
130
50
100
200
350
80
150
60
110
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
PULSE
GENERATOR
14 VDD
INPUT
*
OUTPUT
CL
7 VSS
*All unused inputs of AND, NAND gates must be connected to VDD.
All unused inputs of OR, NOR gates must be connected to VSS.
20 ns
20 ns
INPUT
90%
50%
VDD
10%
0V
tPHL
tPLH
OUTPUT
INVERTING tTHL
90%
50%
10%
tTLH
VOH
VOL
tPLH
OUTPUT
tPHL
90%
VOH
NON-INVERTING
50%
10%
VOL
tTLH
tTHL
Figure 1. Switching Time Test Circuit and Waveforms
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