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MC14001BDR2 View Datasheet(PDF) - ON Semiconductor

Part NameDescriptionManufacturer
MC14001BDR2 B-SUFFIX SERIES CMOS GATES ON-Semiconductor
ON Semiconductor ON-Semiconductor
MC14001BDR2 Datasheet PDF : 14 Pages
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MC14001B Series
B-Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
Features
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Lowpower TTL Loads or One Lowpower
Schottky TTL Load Over the Rated Temperature Range.
Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B
PinforPin Replacements for Corresponding CD4000 Series
B Suffix Devices
PbFree Packages are Available
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
0.5 to +18.0
V
0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
55 to +125
°C
Tstg Storage Temperature Range
65 to +150
°C
TL
Lead Temperature
(8Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
MARKING
DIAGRAMS
PDIP14
P SUFFIX
CASE 646
14
MC140xxBCP
AWLYYWWG
1
14
SOIC14
D SUFFIX
CASE 751A
140xxBG
AWLYWW
1
14
TSSOP14
DT SUFFIX
CASE 948G
1
14
14
0xxB
ALYWG
G
SOEIAJ14
F SUFFIX
CASE 965
MC140xxB
ALYWG
1
xx
= Specific Device Code
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = PbFree Package
(Note: Microdot may be in either location)
DEVICE INFORMATION
Device
MC14001B
MC14011B
MC14023B
MC14025B
MC14071B
MC14073B
Description
Quad 2Input NOR Gate
Quad 2Input NAND Gate
Triple 3Input NAND Gate
Triple 3Input NOR Gate
Quad 2Input OR Gate
Triple 3Input AND Gate
MC14081B
MC14082B
Quad 2Input AND Gate
Dual 4Input AND Gate
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
October, 2006 Rev. 6
Publication Order Number:
MC14001B/D
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