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MC14015BCL View Datasheet(PDF) - Motorola => Freescale

Part NameDescriptionManufacturer
MC14015BCL Dual 4-Bit Static Shift Register Motorola
Motorola => Freescale Motorola
MC14015BCL Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 4-Bit Static Shift Register
The MC14015B dual 4–bit static shift register is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. It consists of two identical, independent 4–state
serial–input/parallel–output registers. Each register has independent Clock
and Reset inputs with a single serial Data input. The register states are type
D master–slave flip–flops. Data is shifted from one stage to the next during
the positive–going clock transition. Each register can be cleared when a high
level is applied on the Reset line. These complementary MOS shift registers
find primary use in buffer storage and serial–to–parallel conversion where
low power dissipation and/or noise immunity is desired.
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Edge–Clocked Flip–Flop Design —
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive going edge
of the clock pulse.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD DC Supply Voltage
– 0.5 to + 18.0
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ lin, lout Input or Output Current (DC or Transient),
± 10
mA
per Pin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ PD Power Dissipation, per Package†
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Tstg Storage Temperature
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TL
Lead Temperature (8–Second Soldering)
500
mW
– 65 to + 150
_C
260
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
TRUTH TABLE
C
D
R
Q0
0
0
0
1
0
1
X
0
No Change
X
X
1
0
X = Don’t Care
Qn = Q0, Q1, Q2, or Q3, as applicable.
Qn–1 = Output of prior stage.
Qn
Qn–1
Qn–1
No Change
0
MC14015B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
BLOCK DIAGRAM
Q0
5
7
D
Q1
4
Q2
3
9
C
R Q3
10
6
Q0
13
15
D
Q1
12
Q2
11
1
C
R Q3
2
14
VDD = PIN 16
VSS = PIN 8
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
MC14015B
57
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