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MC100EP32MNR4G View Datasheet(PDF) - ON Semiconductor

Part Name
Description
View to exact match
MC100EP32MNR4G
ON-Semiconductor
ON Semiconductor ON-Semiconductor
MC100EP32MNR4G Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
MC10EP32, MC100EP32
RESET 1
CLK 2
CLK 3
8 VCC
R
7Q
B2
6Q
VBB 4
5 VEE
Figure 1. 8-Lead Pinout (Top View) and Logic
Diagram
Table 1. PIN DESCRIPTION
Pin
Function
CLK, CLK*
ECL Clock Inputs
Reset*
ECL Asynchronous Reset
VBB
Q, Q
Reference Voltage Output
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
EP
(DFN8 only) Thermal exposed pad
must be connected to a sufficient thermal
conduit. Electrically connect to the most
negative supply (GND) or leave uncon-
nected, floating open.
*Pins will default LOW when left open.
Table 2. TRUTH TABLE
CLK
CLK
RESET
Q
Q
X
X
Z
Z
Z
L
L
H
F
F
Z = LOW to HIGH Transition
Z = HIGH to LOW Transition
F = Divide by 2 Function
CLK
tRR
RESET
Q
Figure 2. Timing Diagram
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC8 NB
TSSOP8
DFN8
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
75 kW
N/A
> 4 kV
> 200 V
> 2 kV
Pb-Free Pkg
Level 1
Level 3
Level 1
UL 94 V0 @ 0.125 in
78 Devices
www.onsemi.com
2
 

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