MC100EP31MNR4G View Datasheet(PDF) - ON Semiconductor
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MC100EP31MNR4G Datasheet PDF : 11 Pages
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MC10EP31, MC100EP31
SET 1
D2
CLK 3
RESET 4
S
D
Flip Flop
R
8 VCC
7Q
6Q
5 VEE
Figure 1. 8−Lead Pinout (Top View) and
Logic Diagram
Table 1. PIN DESCRIPTION
Pin
Function
CLK*
ECL Clock Inputs
Reset*
ECL Asynchronous Reset
Set*
ECL Asynchronous Set
D*
ECL Data Input
Q, Q
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
EP
Exposed pad must be connected to a
sufficient thermal conduit. Electrically
connect to the most negative supply or
leave floating open.
*Pins will default LOW when left open.
Table 2. TRUTH TABLE
D
SET
RESET
L
L
L
H
L
L
X
H
L
X
L
H
X
H
H
Z = LOW to HIGH Transition
CLK
Z
Z
X
X
X
Q
L
H
H
L
UNDEF
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
TSSOP−8
DFN8
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
75 kW
N/A
> 4 kV
> 200 V
> 2 kV
Pb Pkg
Pb−Free Pkg
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
UL 94 V−0 @ 0.125 in
75 Devices
http://onsemi.com
2
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