MC100LVEP14DTR2G View Datasheet(PDF) - ON Semiconductor

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MC100LVEP14DTR2G

2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver

ON Semiconductor 

MC100LVEP14

Table 8. DC CHARACTERISTICS, HSTL VCC = 2.375 V to 3.8 V, VEE = 0 V

−40°C

25°C

85°C

Symbol

Characteristic

Min Typ Max Min Typ Max Min Typ Max Unit

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

1200

1200

400

1200

400

mV

400 mV

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

Table 9. AC CHARACTERISTICS VCC = 0 V, VEE = −2.375 V to −3.8 V or VCC = 2.375 V to 3.8 V; VEE = 0 V (Note 14)

−40°C

25°C

85°C

Symbol

Characteristic

Min Typ Max Min Typ Max Min Typ Max Unit

VOUTPP Output Voltage Amplitude @ 2.5 GHz 330 425

280 375

230 295

mV

(Figure 2)

tPLH

Propagation Delay to

tPHL

Output Differential

300 375 425 300 400 475 300 430 525 ps

tskew

Within−Device Skew (Note 15)

Device−to−Device Skew (Note 15)

10

25

100 125

15

25

150 175

15

25

ps

200 225

ts

Setup Time

th

Hold Time

EN 100 50

100 50

100 50

ps

EN 200 140

200 140

200 140

tJITTER

CLOCK Random Jitter (RMS)

@ v 1.0 GHz

@ v 1.5 GHz

@ v 2.0 GHz

@ v 2.5 GHz

0.157 0.3

0.163 0.2

0.180 0.3

0.179 0.3

0.181 0.3

0.176 0.3

0.201 0.3

0.208 0.3

ps

0.212 0.3

0.218 0.3

0.235 0.3

0.253 0.4

VPP

Minimum Input Swing

150 800 1200 150 800 1200 150 800 1200 mV

tr/tf

Output Rise/Fall Time (20%−80%)

125 165 225 125 180 250 125 200 275 ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.

15. Skew is measured between outputs under identical transitions.

Resource Reference of Application Notes

AN1405/D − ECL Clock Distribution Techniques

AN1406/D − Designing with PECL (ECL at +5.0 V)

AN1503/D − ECLinPSt I/O SPiCE Modeling Kit

AN1504/D − Metastability and the ECLinPS Family

AN1568/D − Interfacing Between LVDS and ECL

AN1672/D − The ECL Translator Guide

AND8001/D − Odd Number Counters Design

AND8002/D − Marking and Date Codes

AND8020/D − Termination of ECL Logic Devices

AND8066/D − Interfacing with ECLinPS

AND8090/D − AC Characteristics of ECL Devices

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