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MC100EPT26DR2 View Datasheet(PDF) - ON Semiconductor

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MC100EPT26DR2 Datasheet PDF : 9 Pages
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MC100EPT26
3.3V 1:2 Fanout Differential
LVPECL/LVDS to LVTTL
Translator
Description
The MC100EPT26 is a 1:2 Fanout Differential LVPECL/LVDS to
LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are
used only +3.3 V and ground are required. The small outline 8lead
package and the 1:2 fanout design of the EPT26 makes it ideal for
applications which require the low skew duplication of a signal in a
tightly packed PC board.
The VBB output allows the EPT26 to be used in a singleended input
mode. In this mode the VBB output is tied to the D0 input for a
noninverting buffer or the D0 input for an inverting buffer. If used,
the VBB pin should be bypassed to ground with > 0.01 mF capacitor.
For a singleended direct connection, use an external voltage
reference source such as a resistor divider. Do not use VBB for a
singleended direct connection or port to another device.
Features
1.4 ns Typical Propagation Delay
Maximum Frequency > 275 MHz Typical
The 100 Series Contains Temperature Compensation
Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
24 mA TTL outputs
Q Outputs Will Default LOW with Inputs Open or at VEE
VBB Output
PbFree Packages are Available
http://onsemi.com
8
1
8
1
SO8
D SUFFIX
CASE 751
TSSOP8
DT SUFFIX
CASE 948R
MARKING
DIAGRAMS*
8
KPT26
ALYW
G
1
8
KA26
ALYWG
G
1
DFN8
MN SUFFIX
CASE 506AA
1
3W MG
G
4
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
November, 2006 Rev. 14
Publication Order Number:
MC100EPT26/D
 

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