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MC100EPT25DTR2 View Datasheet(PDF) - ON Semiconductor

Part Name
Description
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MC100EPT25DTR2 Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
MC100EPT25
−3.3V / −5V Differential ECL
to +3.3V LVTTL Translator
Description
The MC100EPT25 is a Differential ECL to LVTTL translator. This
device requires +3.3 V, 3.3 V to 5.2 V, and ground. The small
outline 8lead package and the single gate of the EPT25 make it ideal
for applications which require the translation of a clock or data signal.
The VBB output allows the EPT25 to also be used in a singleended
input mode. In this mode the VBB output is tied to the D input for a
inverting buffer or the D input for a noninverting buffer. If used, the
VBB pin should be bypassed to ground with at least a 0.01 mF
capacitor.
Features
1.1 ns Typical Propagation Delay
Maximum Frequency > 275 MHz Typical
Operating Range: VCC = 3.0 V to 3.6 V;
VEE = 5.5 V to 3.0 V; GND = 0 V
24 mA TTL Outputs
Q Output Will Default LOW with Inputs Open or at VEE
VBB Output
Open Input Default State
Safety Clamp on Inputs
PbFree Packages are Available
http://onsemi.com
8
1
SOIC8
D SUFFIX
CASE 751
MARKING DIAGRAMS*
8
KPT25
ALYW
G
1
8
1
TSSOP8
DT SUFFIX
CASE 948R
8
KP25
ALYWG
G
1
DFN8
MN SUFFIX
CASE 506AA
14
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
December, 2006 Rev. 14
Publication Order Number:
MC100EPT25/D
 

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