MC100EPT22
Q0 1
Q0 2
Q1 3
LVPECL
8 VCC
7 D0
LVTTL
6 D1
Q1 4
5 GND
Figure 1. 8−Lead Pinout (Top View) and Logic Diagram
Table 1. PIN DESCRIPTION
PIN
FUNCTION
Q0, Q1, Q0, Q1 LVPECL Differential Outputs
D0, D1
VCC
GND
LVTTL Inputs
Positive Supply
Ground
EP
Exposed pad must be con-
nected to a sufficient thermal
conduit. Electrically connect to
the most negative supply or
leave floating open.
Table 2. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
TSSOP−8
DFN8
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
N/A
N/A
> 4 kV
> 200 V
> 2 kV
Pb Pkg
Pb−Free Pkg
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
UL 94 V−0 @ 0.125 in
164 Devices
http://onsemi.com
2