MBM29F017A-12PFTN View Datasheet(PDF) - Fujitsu

Part Name

Description

View to exact match

MBM29F017A-12PFTN

FLASH MEMORY CMOS 16M (2M × 8) BIT

Fujitsu 

MBM29F017A-70/-90/-12

s AC CHARACTERISTICS

• Read Only Operations Characteristics

Parameter

Symbols

JEDEC Standard

Description

Test Setup

-70

(Note1)

-90

(Note2)

-12

(Note2)

Unit

tAVAV

tRC

Read Cycle Time

— Min. 70

90

120 ns

tAVQV

tACC

Address to Output Delay

CE = VIL

OE = VIL

Max.

70

90

120 ns

tELQV

tCE

Chip Enable to Output Delay

OE = VIL Max. 70

90

120 ns

tGLQV

tOE

Output Enable to Output Delay

— Max. 40

40

50 ns

tEHQZ

tDF

Chip Enable to Output High-Z

— Max. 20

20

30 ns

tGHQZ

tDF

Output Enable to Output High-Z

— Max. 20

20

30 ns

tAXQX

tOH

Output Hold Time From Addresses, CE

or OE, whichever occurs first

—

Min.

0

0

0 ns

—

tREADY

RESET Pin Low to Read Mode

— Max. 20

20

20 µs

Note: 1. Test Conditions:

Output Load: 1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level

Input: 1.5 V

Output: 1.5 V

Note: 2. Test Conditions:

Output Load: 1 TTL gate and 100 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.45 V to 2.4 V

Timing measurement reference level

Input: 0.8 V and 2.0 V

Output: 0.8 V and 2.0 V

Device

Under

Test

CL

5.0 V

IN3064

or Equivalent

2.7 kΩ

6.2 kΩ

Diodes = IN3064

or Equivalent

Note: 1. CL = 30 pF including jig capacitance

2. CL = 100 pF including jig capacitance

Figure 4 Test Conditions

25

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