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MB15E03SL View Datasheet(PDF) - Fujitsu

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MB15E03SL Datasheet PDF : 32 Pages
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Single PLL Frequency Synthesizers with On-Chip Prescalers
Phase Detector Output Waveform
fr
fp
LD
(FC bit = High)
Do
(FC bit = Low)
Do
tWU
H
Z
Z
tWL
L
Notes:
1) Phase error detection range: –2π to +2π
2) Pulses on Do signal during locked state are output to prevent dead zone.
3) LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL
or less and continues to be so for three cycles or more.
4) tWU and tWL depend on OSCIN input frequency.
tWU > 2/fosc (s) (e. g. tWU > 156.3ns, fosc = 12.8MHz)
tWU < 4/fosc (s) (e. g. tWL < 312.5ns, fosc = 12.8MHz)
5) LD becomes high during the power-saving mode (PS = “L”).
26 Fujitsu Microelectronics, Inc.
 

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