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MB15E03SL View Datasheet(PDF) - Fujitsu

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MB15E03SL Datasheet PDF : 32 Pages
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Single PLL Frequency Synthesizers with On-Chip Prescalers
Functional Descriptions
Serial Data Input
The VCO output frequency can be calculated using the following
equation:
fVCO = {(M x N) + A} x fOSC ÷ R (A < N)
fVCO Output frequency of external voltage controlled ocillator (VCO)
M Preset divide ratio of dual modulus prescaler (64 or 128 for
MB15E03SL, MB15E05SL) (32 or 64 for MB15E07SL)
N Preset divide ratio of binary 11-bit programmable counter
(3 to 2,047)
A Preset divide ratio of binary 7-bit swallow counter (0 A 127)
fOSC Reference oscillation frequency
R Preset divide ratio of binary 14-bit programmable reference
counter (3 to 16,383)
Serial data is entered using the Data, Clock and LE pins.The serial
data controls the programmable reference counters and the
programmable counters separately.
Binary serial data is entered through the Data pin when the LE pin
is held low. One bit of data is shifted into the shift register on the
rising edge of the Clock. When the LE signal pin is taken high,
entered data is latched into the appropriate counters according to
the control bit settings as follows:
Table 1. Control Bits
Control Bit (CNT)
H
L
Destination of Serial Data
Programmable reference counter latch
Programmable counter latch
Shift Register Configuration
Programmable Reference Counter
LSB
Data Flow
MSB
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
CRRRRRRRRRRRRRR
N
1
2
3
4
5
6
7
8
9 10 11 12 13 14 SW FC LDS CS
T
CNT
R1 to R14
SW
FC
LDS
CS
Control bit
Divide ratio setting bits for the programmable reference counter (3 to 16,383)
Divide ratio setting bit for the prescaler
Phase control bit for the phase comparator
LD/fOUT signal select bit
Charge pump current select bit
Note: Input data with MSB first.
[Table 1]
[Table 2]
[Table 5]
[Table 6]
[Table 7]
[Table 8]
20 Fujitsu Microelectronics, Inc.
 

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