MAX9880A View Datasheet(PDF) - Maxim Integrated

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MAX9880A

Low-Power, High-Performance Dual I2S Stereo Audio Codec

Maxim Integrated 

Low-Power, High-Performance

Dual I2S Stereo Audio Codec

Table 11. SPDM Output Registers

REGISTER

Configuration

Input

B7

B6

B5

B4

B3

SPDMCLK

SPDML SPDMR

0

MIXSPDML

B2

B1

0

0

MIXSPDMR

REGISTER

B0

ADDRESS

(SEE NOTE)

0

0x12

0x13

Grayed boxes = Not used.

Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not

accessible through SPI.

The MAX9880A supports stereo PDM outputs. The PDM

signals consist of PDM data outputs (SPDMDATA) and a

clock output (SPDMCLK). The mixer at the input to the

PDM modulators allows a mix/mux of the audio digital data

stream from the digital audio ports SDINS1 and SDINS2.

Figure 5 shows the SPDM interface timing diagram.

SPDMCLK

tDLY, DSD

tDLY, DSD

SPDMDATA LEFT CH

RIGHT CH

LEFT CH

RIGHT CH

Figure 5. SPDM Timing Diagram

BITS

SPDMCLK

SPDML/SPDMR

MIXSPDML/

MIXSPDMR

FUNCTION

SPDM Clock Rate (SPDMCLK)

00 = SPDMCLK is set to PCLK/8.

01 = SPDMCLK is set to PCLK6.

10 = SPDMCLK is set to PCLK/4.

11 = Reserved

0 = Disables SPDM data.

1 = Enables SPDM data.

SPDM Input Mixers. Selects and mixes the audio source(s) for the SPDM output according to following

information.

MIXSPDML/MIXSPDMR

1xxx

x1xx

xx1x

xxx1

SOURCE

DAI1 left-channel data

DAI1 right-channel data

DAI2 left-channel data

DAI2 right-channel data

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