MAX9880A View Datasheet(PDF) - Maxim Integrated
Part Name
Description
View to exact match
MAX9880A Datasheet PDF : 70 Pages
| |||
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Hardware Interrupts
Hardware interrupts are reported on the open-drain IRQ
pin. When an interrupt occurs, IRQ remains low until the
interrupt is serviced by reading the status register 0x00.
If a flag is set, it is reported as a hardware interrupt only
if the corresponding interrupt enable is set. Each bit
enables interrupts for the status flag in the respective
bit location in register 0x00.
Table 4. Interrupt Enable
REGISTER
Interrupt Enable
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS
(SEE NOTE)
ICLD
ISLD
IULK
0
0*
0*
IJDET
0
0x04
*Reserved.
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
Clock Control
The MAX9880A can work with a master clock (MCLK)
supplied from any system clock within the 10MHz to
60MHz range. Internally the MAX9880A requires a
10MHz to 20MHz clock. A prescaler divides MCLK by
1, 2, or 4 to create the internal clock (PCLK). PCLK is
used to clock all portions of the MAX9880A.
The MAX9880A can support any sample rate from 8kHz
to 48kHz for the digital audio path DAI1 (DAC and
ADC) and 8kHz to 96kHz for the DAI2 (high-fidelity
DAC path), including all common sample rates (8kHz,
16kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 96kHz). To
accommodate a wide range of system architectures,
the MAX9880A supports three main clocking modes:
• Normal mode: This mode uses a 15-bit clock
divider coefficient to set the sample rate relative to
the prescaled MCLK input (PCLK). This allows high
flexibility in both the MCLK and LRCLK frequencies
and can be used in either master or slave mode.
• Exact integer mode: Common MCLK frequencies
(12MHz, 13MHz, 16MHz, and 19.2MHz) can be pro-
grammed to operate in exact integer mode for both
8kHz and 16kHz sample rates. In these modes, the
MCLK and LRCLK rates are selected by using the
FREQ1 bits instead of the NI high, NI low, and PLL con-
trol bits.
• PLL mode: When operating in slave mode, a PLL
can be enabled to lock onto externally generated
LRCLK signals that are not integer related to PCLK.
Prior to enabling the interface, program NI to the
nearest desired ratio and set the NI[0] = 1 to enable
the PLL’s rapid lock mode. If NI[0] = 0, then NI is
ignored and PLL lock time is slower.
Table 5. System and Audio Clock Registers
REGISTER
B7
B6
B5
B4
B3
B2
B1
REGISTER
B0
ADDRESS
(SEE NOTE)
SYSTEM CLOCK CONTROL
System Clock
0
0
PSCLK
FREQ1
0x05
DAI1 CLOCK CONTROL
Stereo Audio Clock Control High PLL1
NI1[14:8]
0x06
Stereo Audio Clock Control Low
NI1[7:1]
RLK1/NI1[0] 0x07
DAI2 CLOCK CONTROL
Stereo Audio Clock Control High PLL2
NI2[14:8]
0x0B
Stereo Audio Clock Control Low
NI2[7:1]
RLK2/NI2[0] 0x0C
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
30 ______________________________________________________________________________________
|
|
Share Link: 